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Functional Architecture

Intel® Compute Module MFS5520VI TPS

Revision

1.5

Intel order number: E64311-007

Functional Architecture

The architecture and design of the Intel

Compute Module MFS5520VI is based on the Intel

5520 Chipset I/O Hub (IOH) and the Intel

82801JR ICH10 RAID. The chipset is designed for

systems based on the Intel

Xeon

Processor in FC-LGA 1366 socket B package with Intel

QuickPath Interconnect (Intel

QPI). The chipset contains two main components:

Intel

5520 Chipset I/O Hub (IOH) that provides a connection point between various I/O

components.

Intel

82801JR, which is the I/O controller hub (ICH10R) for the I/O subsystem.

This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up the server board

Primary

Mid-Plane Connector

FLASH

TPM

Opt - int in TB

DRAM

BMC

SSI Compliant

Mezzanine

Flex IO

Connector

Figure 4. Intel

Compute Module MFS5520VI Functional Block Diagram

Содержание MFS5520VI - Multi-Flex Server Compute Module

Страница 1: ...Intel Compute Module MFS5520VI Technical Product Specification Intel order number E64311 007 Revision 1 5 December 2010 Enterprise Platforms and Services Division...

Страница 2: ...ristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising f...

Страница 3: ...QuickPath Interconnect 9 3 1 6 Unified Retention System Support 10 3 2 Memory Subsystem 11 3 2 1 Intel QuickPath Memory Controller 11 3 2 2 Publishing Compute Module Memory 11 3 2 3 Memory Map and Pop...

Страница 4: ...Jumper Blocks 31 5 1 1 CMOS Clear and Password Clear Usage Procedure 32 5 1 2 Integrated BMC Force Update Procedure 32 5 1 3 Integrated BMC Initialization 33 6 Product Regulatory Requirements 34 6 1 P...

Страница 5: ...Front Panel Layout 4 Figure 3 Intel Compute Module MFS5520VI Hole and Component Positions 5 Figure 4 Intel Compute Module MFS5520VI Functional Block Diagram 6 Figure 5 Unified Retention System and Uni...

Страница 6: ...3 Table 7 Power Connector Pin out J1A1 23 Table 8 VGA Connector Pin out J6A1 24 Table 9 120 pin I O Mezzanine Card Connector Pin out 25 Table 10 120 pin I O Mezzanine Card Connector Signal Definitions...

Страница 7: ...Intel Compute Module MFS5520VI TPS List of Tables Revision 1 5 vii Intel order number E64311 007 This page intentionally left blank...

Страница 8: ...Post Error Messages and Handling Appendix D Supported Intel Modular Server System Glossary Reference Documents 1 2 Intel Compute Module Use Disclaimer Intel Modular Server components require adequate...

Страница 9: ...6 1333 MT s ECC registered RDIMM or unbuffered UDIMM DDR3 memory 12 DIMMs total across 6 memory channels 3 channels per processor Note Mixed memory is not tested or supported Non ECC memory is not tes...

Страница 10: ...H P O N L M A C E D I K M A Intel 5520 Chipset I O Hub J CPU 2 Socket B CPU2 DIMM Slots K Power Fault LEDs C Mezzanine Card Connector 1 L Power Switch D CPU 1 with Heatsink M Activity and ID LEDs E Me...

Страница 11: ...E64311 007 4 AF003120 A C B H I D E F G A USB ports 0 and 1 F Hard Drive Activity LED B USB ports 2 and 3 G ID LED C Video H Power button D I O Mezzanine NIC ports 1 and 2 LEDs I Power and Fault LEDs...

Страница 12: ...256 54 262 89 6 35 72 65 169 85 185 93 203 78 213 94 224 10 234 26 244 42 254 58 148 40 102 02 138 84 248 92 10 16 396 24 300 35 41 40 141 77 115 85 98 85 166 99 173 99 223 39 209 52 192 99 185 99 23...

Страница 13: ...ath Interconnect Intel QPI The chipset contains two main components Intel 5520 Chipset I O Hub IOH that provides a connection point between various I O components Intel 82801JR which is the I O contro...

Страница 14: ...ame front side bus speed Both processors must have the same cache size Processors with different speeds can be mixed in a system given the prior rules are met If this condition is detected all process...

Страница 15: ...match detected message in the Error Manager Takes Fatal Error action see above and will not boot until the fault condition is remedied Processor frequency speed not identical Fatal The BIOS detects th...

Страница 16: ...The default is enabled 3 1 5 Intel QuickPath Interconnect Intel QPI is a cache coherent link based interconnect specification for processor chipset and I O bridge components Intel QPI provides suppor...

Страница 17: ...le through the unified backplate assembly The URS spring captive in the heatsink provides the necessary compressive load for the thermal interface material All components of the URS heatsink solution...

Страница 18: ...e Module MFS5520VI Mixing of RDIMMs and UDIMMs is not supported Mixing memory type size speed and or rank on this server board is not validated and is not supported Mixing memory vendors is not valida...

Страница 19: ...nnel C Channel D Channel E Channel F A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 Figure 6 DIMM Nomenclature AF003098 DIMM B2 DIMM A1 DIMM A2 DIMM B1 DIMM C2 DIMM C1 DIMM F1 DIMM F2 DIMM E1 DIMM D2 DIMM D1 DIM...

Страница 20: ...l B mirrors channel A All DIMM matching requirements are on a slot to slot basis on adjacent channels For example to enable mirroring corresponding slots on channel A and channel B must have DIMMs of...

Страница 21: ...irroring is enabled the BIOS attempts to configure the memory system accordingly If the BIOS finds that the DIMM population is not suitable for mirroring it falls back to the default Channel Independe...

Страница 22: ...erate independently The Channel Independent mode can also be used to support a single DIMM configuration in channel A and in the single channel mode The following general rules must be observed when s...

Страница 23: ...s installing DIMM_B1 to allow channel interleaving The system operates in the Independent Channel mode The DIMM parameter matching requirements for memory RAS is local to a socket For example while Ch...

Страница 24: ...tel QPI PCI Express Gen2 Intel I O Acceleration Technology 2 Intel I OAT2 Intel Virtualization Technology Intel VT for Directed I O 2 Intel VT d2 3 4 Intel 82801JR I O Controller Hub ICH10R The Intel...

Страница 25: ...ent Characteristics PCI Bus Segment Voltage Width Speed Type PCI I O Card Slots ESI or DMI Port 0 ICH10R 3 3 V x4 10 Gb s PCI Express Gen1 x4 PCI Express Gen1 throughput to the Intel 5520 Chipset IOH...

Страница 26: ...0 Mhz 32 bit ARM9 processor Six I2 C SMBus modules with Master Slave support Two independent 10 100 Ethernet Controllers with RMII support Memory Management Unit MMU DDR2 16 bit up to 667 MHz memory i...

Страница 27: ...chitecture Intel Compute Module MFS5520VI TPS Revision 1 5 Intel order number E64311 007 20 2D Graphics Acceleration DDR2 graphics memory interface Up to 1600x1200 pixel resolution Figure 8 Integrated...

Страница 28: ...both CRT and LCD monitors up to a 100 Hz vertical refresh rate The video is accessed using a standard 15 pin VGA connector found on the front panel of the compute module 3 6 1 Video Modes The integrat...

Страница 29: ...mize cache misses when a demand read is executed This is accomplished by placing the data from the I O devices directly into the CPU cache through hints to the processor to perform a data pre fetch an...

Страница 30: ...ators printed on the silkscreen Table 6 Board Connector Matrix Connector Quantity Reference Designators Power Connector 1 J1K1 Midplane Signal Connector 1 J1H1 CPU 2 CPU1 U2D2 CPU2 U7C1 Main Memory 12...

Страница 31: ...r signal B 4 TP_VID_CONN_B4 No connection 5 GND Ground 6 GND Ground 7 GND Ground 8 GND Ground 9 P5V_VID_CONN_9 P5V 10 GND Ground 11 TP_VID_CONN_B11 No connection 12 V_IO_DDCDAT DDCDAT 13 V_IO_HSYNC_CO...

Страница 32: ...7 WAKE_N 28 Rsvd 29 GND 30 Rsvd 31 GND 32 GND 33 PCIe_0_A_TXP 34 GND 35 PCIe_0_A_TXN 36 PCIe_0_A_RXP 37 GND 38 PCIe_0_A_RXN 39 GND 40 GND 41 PCIe_0_B_TXP 42 GND 43 PCIe_0_B_TXN 44 PCIe_0_B_RXP 45 GND...

Страница 33: ...PCIe_0_B_TXN PCIe TX of Lane B Link 0 Host connect 44 PCIe_0_B_RXP PCIe RX of Lane B Link 0 Host connect 45 PCIe_0_B_RXN PCIe RX of Lane B Link 0 Host connect 47 PCIe_0_C_TXP PCIe TX of Lane C Link 0...

Страница 34: ...0 Link LED driver LED control 19 HSC_1_LNK_LED HSC 1 Link LED driver LED control 21 HSC_2_LNK_LED HSC 2 Link LED driver LED control 23 HSC_3_LNK_LED HSC 3 Link LED driver LED control 25 HSC_0_ACT_LED...

Страница 35: ...IOME ZZ_TXD1 36 RMII_IBMC_IOMEZZ _RXD1 37 RMII_IBMC_IOME ZZ_TXD0 38 RMII_IBMC_IOMEZZ _RXD0 39 CLK_IOMEZZ_RMI I 40 4 3 3 Midplane Signal Connector The compute module connects to the midplane through a...

Страница 36: ...GND D2 GND H2 SAS_P1_TXP L2 FM_BL_SLOT_ID1 D3 SMB_SCL_B H3 XE_P2_C_RXN L3 GND D4 GND H4 XE_P2_C_TXP L4 FM_BL_PRES_N D5 XE_P2_B_RXP H5 SAS_P2_RXN L5 GND D6 GND H6 SAS_P2_TXP L6 reserved D7 XE_P2_A_RXP...

Страница 37: ...ATAH0 3 USB_P Differential data line paired with DATAL0 4 GND Ground One low profile 2x5 connector J9B7 on the compute module provides an option to support low profile Intel Z U130 Value Solid State D...

Страница 38: ...used to configure protect or recover specific features of the server board Pin 1 on each jumper block is denoted by an or 5 1 Recovery Jumper Blocks BMC Force Update J9A5 3 2 Default Disabled Enabled...

Страница 39: ...system downtime The usage procedure for these two features has changed from previous generation Intel server boards The following procedure outlines the new usage model 1 Power down the compute modul...

Страница 40: ...r up the compute module Note Normal Integrated BMC functionality for example KVM monitoring and remote media is disabled with the force BMC update jumper set to the Enabled position The server should...

Страница 41: ...tem and component regulatory requirements 6 2 Product Regulatory Compliance and Safety Markings No markings are required on the Intel Compute Module MFS5520VI itself as it is evaluated as part of the...

Страница 42: ...or memory vendors is not validated and is not supported on this server board Non ECC memory is not validated and is not supported in a server environment For the best performance the number of DDR3 D...

Страница 43: ...fic type of discrete sensors which have only two states Event Offset Triggers This column defines what event offsets the sensor generates For Threshold analog reading type sensors the Integrated BMC c...

Страница 44: ...or is one example These sensors operate by asserting and then immediately de asserting an event Typically the SDRs for such sensors are defined such that only the assertion causes an event message to...

Страница 45: ...2h Sensor Specific 6Fh OK A BB 1 1V IOH 10h Voltage 02h Threshold 01h u l c nc nc Degraded c Non fatal A BB 1 1V P1 Vccp 11h Voltage 02h Threshold 01h u l c nc nc Degraded c Non fatal A BB 1 1V P2 Vcc...

Страница 46: ...graded c Non fatal A MEM P2 Thermal Margin 24h Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal A DIMM Max temp 2Fh Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal A 01 Th...

Страница 47: ...Deactivation Required None Hot Swap 70h FRU State 2Ch Sensor Specific 6Fh 6 Deactivation In Progress None A X 0 Pending None 1 Established None 2 Ended Normally None 3 Ticket Expiration None 4 Lost h...

Страница 48: ...Event Reading Type Event Offset Triggers Contrib To System Status Rearm Stand by 08h 1 Device Present Drive 1 2 C3h C4h Drive Slot 0Dh Sensor Specific 6Fh None A Slot ID C5h OEM D1h Threshold 01h Non...

Страница 49: ...setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to continue booting Fatal The message is displaye...

Страница 50: ...jor 8529 DIMM_E2 failed Self Test BIST Major 852A DIMM_F1 failed Self Test BIST Major 852B DIMM_F2 failed Self Test BIST Major 8540 DIMM_A1 Disabled Major 8541 DIMM_A2 Disabled Major 8542 DIMM_B1 Disa...

Страница 51: ...le component encountered a controller error Minor 9268 Local Console component encountered an output error Minor 9269 Local Console component encountered a resource conflict error Minor 9286 Remote Co...

Страница 52: ...disabled Minor 0xA5A0 PCI Express component encountered a PERR error Minor 0xA5A1 PCI Express component encountered a SERR error Fatal 0xA5A4 PCI Express IBIST error Major 0xA6A0 DXE boot services dri...

Страница 53: ...System MFSYS25 Intel Modular Server System MFSYS25V2 Intel Modular Server System MFSYS35 This section provides a high level pictorial overview of the Intel Modular Server System MFSYS25 For more deta...

Страница 54: ...hassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis CEK Common Enabling Kit CHAP Challenge Handshake Authentication P...

Страница 55: ...iplexor NIC Network Interface Controller NMI Non maskable Interrupt OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance PEF Platform Event Filtering PEP Platform Ev...

Страница 56: ...interrupt SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver Tra...

Страница 57: ...Documents Intel Compute Module MFS5520VI TPS Revision 1 5 Intel order number E64311 007 50 Reference Documents For additional information refer to the Intel Modular Server System Technical Product Spe...

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