Functional Architecture
Intel® Compute Module MFS5520VI TPS
Revision
1.5
Intel order number: E64311-007
16
The memory operational mode is configurable at the channel level. Two modes are
supported: Independent Channel and Mirrored Channel.
The memory slots of each DDR3 channel from the Intel
®
Xeon
®
Processor 5500 series
and Intel
®
Xeon
®
Processor 5600 series are populated on a farthest first fashion. This
holds true even for the Independent Channel mode. Therefore, if A1 is empty, A2 cannot
be populated or used.
The BIOS selects Independent Channel mode by default, which enables all installed
memory on all channels simultaneously.
Mirrored Channel mode is not available when only one processor is populated (CPU
Socket 1).
If both processor sockets are populated and the installed DIMMs are associated with
both processor sockets, then a given RAS mode is selected only if both the processor
sockets are populated to conform to that mode.
The minimum memory population possible is one DIMM in slot A1. In this configuration,
the system operates in the Independent Channel mode. RAS is not available.
If both processor sockets are populated, the next upgrade from the Single Channel
mode installs DIMM_D1. This configuration results in an optimal memory thermal
spread, as well as Non-Uniform Memory Architecture (NUMA) aware interleaving. The
BIOS selects the Independent Channel mode of operation.
If only one processor socket is populated, the next upgrade from the Single Channel
mode is installing DIMM_B1 to allow channel interleaving. The system operates in the
Independent Channel mode.
The DIMM parameter-matching requirements for memory RAS is local to a socket. For
example, while Channels A/B/C can have one match of timing, technology, and size,
Channels D/E/F can have a different set of parameters and RAS still functions.
For the Mirrored Channel mode, the memory in Channels A and B of Socket 1 must be
identical and Channel C should be empty. Similarly, the memory in Channels D and E of
Socket 2 must be identical and Channel F should be empty.
a. The minimum population upgrade for the Mirrored Channel mode is DIMM_A1,
DIMM_B1, DIMM_D1, and DIMM_E1 with both processor sockets populated.
DIMM_A1 and DIMM_B1 as a pair must be identical, and so must DIMM_D1 and
DIMM_E1. Failing to comply with these rules results in a switch back to the
Independent Channel mode.
b. If Mirrored Channel mode is selected and the third channel of each processor socket
is not empty, the BIOS disables the memory in the third channel of each processor
socket.
In the Mirrored Channel mode, both sockets must simultaneously satisfy the DIMM
matching rules on their respective adjacent channels. If the DDR3 DIMMs on adjacent
channels of a socket are not identical, the BIOS configures both of the processor
sockets to default to the Independent Channel mode. If DIMM_D1 and DIMM_E1 are not
identical, then the system switches to the Independent Channel Mode.
Note:
Mixed memory size, type, speed, rank and/or vendor is not validated or supported
with the Intel
®
Compute Module MFS5520VI. Refer to section 3.2.1.1 for supported and
nonsupported memory features and configuration information.
