Errata
Specification Update
53
Workaround:
If use of the on-demand mode of the processor's TCC is desired in conjunction
with STPCLK# modulation, then assure that STPCLK# is not asserted at a 12.5%
duty cycle.
Status:
For the steppings affected, see the
Summary Tables of Changes.
61.
System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL)
Transaction to Occur to the Same Cache Line Address as an
Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL)
Problem:
A processor internal cache fatal data ECC error may cause the processor to issue a
BWL transaction to the same cache line address as an outstanding BRL or BRIL. As it
is not typical behavior for a single processor to have a BWL and a BRL/BRIL
concurrently outstanding to the same address, this may represent an unexpected
scenario to system logic within the chipset.
Implication:
The processor may not be able to fully execute the machine check handler in
response to the fatal cache error if system logic does not ensure forward progress on
the system bus under this scenario.
Workaround:
System logic should ensure completion of the outstanding transactions. Note that
during recovery from a fatal data ECC error, memory image coherency of the BWL
with respect to BRL/BRIL transactions is not important. Forward progress is the
primary requirement.
Status:
For the steppings affected, see the
Summary Tables of Changes.
62.
L2 Cache May Contain Stale Data in the Exclusive State
Problem:
If a cacheline (A) is in Modified (M) state in the write-combining (WC) buffers and in
the Invalid (I) state in the L2 cache and its adjacent sector (B) is in the Invalid (I)
state and the following scenario occurs:
1.
A read to B misses in the L2 cache and allocates cacheline B and its associated
second-sector pre-fetch into an almost full bus queue,
2.
A Bus Read Line (BRL) to cacheline B completes with HIT# and fills data in
Shared (S) state,
3.
The bus queue full condition causes the prefetch to cacheline A to be cancelled,
cacheline A will remain M in the WC buffers and I in the L2 while cacheline B will
be in the S state.
Then, if the further conditions occur:
1.
Cacheline A is evicted from the WC Buffers to the bus queue which is still almost
full,
2.
A hardware prefetch Read for Ownership (RFO) to cacheline B, hits the S state in
the L2 and observes cacheline A in the I state, allocates both cachelines,
3.
An RFO to cacheline A completes before the WC Buffers write modified data back,
filling the L2 with stale data,
4.
The writeback from the WC Buffers completes leaving stale data, for cacheline A,
in the Exclusive (E) state in the L2 cache.
Implication:
Stale data may be consumed leading to unpredictable program execution. Intel has
not been able to reproduce this erratum with commercial software.
