Errata
50
Specification
Update
Workaround:
Do not place page directories and/or page tables in WC memory.
Status:
For the steppings affected, see the
Summary Tables of Changes.
51.
Buffer on Resistance May Exceed Specification
Problem:
The datasheet specifies the resistance range for R
ON
(Buffer On Resistance) for the
AGTL+ and Asynchronous GTL+ buffers as 5 to 11 Ohms. Due to this erratum, R
ON
may be as high as 13.11 Ohms.
Implication:
The R
ON
value affects the voltage level of the signals when the buffer is driving the
signal low. A higher R
ON
may adversely affect the system's ability to meet
specifications such as V
IL
. As the system design also affects margin to specification,
designs may or may not have sufficient margin to function properly with an increased
R
ON
. System designers should evaluate whether a particular system is affected by this
erratum. Designs that follow the recommendations in the
Intel
®
Pentium
®
4
Processor and Intel
®
850 Chipset Platform Design Guide
are not expected to be
affected.
Workaround:
No workaround is necessary for systems with margin sufficient to accept a higher
R
ON
.
Status:
For the steppings affected, see the
Summary Tables of Changes.
52.
Processor Issues Inconsistent Transaction Size Attributes for Locked
Operation
Problem:
When the processor is in the Page Address Extension (PAE) mode and detects the
need to set the Access and/or Dirty bits in the page directory or page table entries,
the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte
store unlock is expected, but instead a 4 byte store unlock occurs. Correct data is
provided since only the lower bytes change, however external logic monitoring the
data transfer may be expecting an 8-byte store unlock.
Implication:
No known commercially available chipsets are affected by this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
53.
Multiple Accesses to the Same S-State L2 Cache Line and ECC Error
Combination May Result in Loss of Cache Coherency
Problem:
When a Read for Ownership (RFO) cycle has a 64-bit address match with an
outstanding read hit on a line in the L2 cache which is in the S-state AND that line
contains an ECC error, the processor should recycle the RFO until the ECC error is
handled. Due to this erratum, the processor does not recycle the RFO and attempts
to service both the RFO and the read hit at the same time.
Implication:
When this erratum occurs, cache may become incoherent.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
