Errata
42
Specification
Update
Problem:
Bit 1 of the IA32_THERM_STATUS register (Thermal Status Log) is a sticky bit
designed to be set to '1' if the thermal control circuit (TCC) has been active since
either the previous processor reset or software cleared this bit. If TCC is active and
the Thermal Status Log bit is cleared by a processor reset or by software, it will
remain clear (set to ‘0’) as long as the TCC remains active. Once TCC deactivates,
the next activation of the TCC will set the Thermal Status Log bit.
Implication:
When this erratum occurs, the Thermal Status Log bit remains cleared (set to ‘0’)
although the thermal control circuit is active.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
37.
Debug Mechanisms May Not Function As Expected
Problem:
Certain debug mechanisms may not function as expected on the processor. The
cases are as follows:
When the following conditions occur: 1) An FLD instruction signals a stack overflow or
underflow, 2) the FLD instruction splits a page-boundary or a 64 byte cache line
boundary, 3) the instruction matches a Debug Register on the high page or cache
line respectively, and 4) the FLD has a stack fault and a memory fault on a split
access, the processor will only signal the stack fault and the debug exception will not
be taken.
When a data breakpoint is set on the ninth and/or tenth byte(s) of a floating point
store using the Extended Real data type, and an unmasked floating point exception
occurs on the store, the break point will not be captured.
When any instruction has multiple debug register matches, and any one of those
debug registers is enabled in DR7, all of the matches should be reported in DR6 when
the processor goes to the debug handler. This is not true during a REP instruction. As
an example, during execution of a REP MOVSW instruction the first iteration a load
matches DR0 and DR2 and sets DR6 as FFFF0FF5h. On a subsequent iteration of the
instruction, a load matches only DR0. The DR6 register is expected to still contain
FFFF0FF5h, but the processor will update DR6 to FFFF0FF1h.
A data breakpoint that is set on a load to uncacheable memory may be ignored due
to an internal segment register access conflict. In this case the system will continue
to execute instructions, bypassing the intended breakpoint. Avoiding having
instructions that access segment descriptor registers, e.g., LGDT, LIDT close to the
UC load, and avoiding serialized instructions before the UC load will reduce the
occurrence of this erratum.
Implication:
Certain debug mechanisms do not function as expected on the processor.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
38.
Machine Check Architecture Error Reporting and Recovery May Not Work As
Expected
