Errata
38
Specification
Update
23.
MCA Error Incorrectly Logged As Prefetches
Problem:
An MCA error is being incorrectly logged as PREFETCH type errors in the Request
sub-field of the Compound error code in the IA32_MC0_STATUS register. A store,
which hits a double bit data error in the L2 cache, is incorrectly logged as a prefetch
data error.
Implication:
When this erratum occurs, the IA32_MC0_STATUS register will contain incorrect
information.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
24.
Speculative Loads Which Hit the L2 Cache and Get an Uncorrectable
Error Will Log Erroneous Information
Problem:
If a speculative load that hits the L2 cache and has an uncorrectable error, the load is
subsequently cancelled, but the processor will still report that it has received an
uncorrectable error via bit 61 of the IA32_MC1_STATUS register. Any other
information in this register will not be associated with this uncorrectable error and is
therefore erroneous.
Implication:
When this erratum occurs, erroneous information is logged in the IA32_MC1_STATUS
register.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
25.
Processor May Fetch Reset Vector from Cache if A20M# Is Asserted
during Init
Problem:
If A20M# is asserted with INIT# or after INIT# but before the first code fetch occurs,
then the processor should fetch the reset vector from the system bus but instead
may fetch the vector from cache.
Implication:
Instead of forcing the fetch from the bus, the processor may fetch the reset vector
from cache.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
26.
A Correctable Error on an L2 Cache Shared State Line Hit with go to
Invalid Snoop Hangs Processor
Problem:
When the following events occur:
•
A read for ownership (RFO) is issued by the processor and hits a line in Shared
(S) state in the L2 cache,
•
The operation also receives a correctable error on the data that is read, and
•
At the same time the RFO is accessing the cache, it is hit by Go to Invalid snoop,
