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Errata

Specification Update

Implication:

An interrupt may immediately be generated with the new vector when a LVT entry is

written, even if the new LVT entry has the mask bit set. If there is no Interrupt

Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does

not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service

Workaround:

Any vector programmed into an LVT entry must have an ISR associated with it,

even if that vector was programmed as masked. This ISR routine must do an EOI to

clear any unexpected interrupts that may occur. The ISR associated with the spurious

vector does not generate an EOI, therefore the spurious vector should not be used

when writing the LVT.

Status:

For the steppings affected, see the

Summary Tables of Changes.

102.

Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations

Problem:

An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)

to emulates real-address mode address wraparound at 1 megabyte. However, if all of

the following conditions are met, address bit 20 may not be masked.

•

Paging is enabled

•

A linear address has bit 20 set

•

The address references a large page

•

A20M# is enabled

Implication:

When A20M# is enabled and an address references a large page the resulting

translated physical address may be incorrect. This erratum has not been observed

with any commercially available operating system.

Workaround:

Operating systems should not allow A20M# to be enabled if the masking of

address bit 20 could be applied to an address that references a large page. A20M# is

normally only used with the first megabyte of memory.

Status:

For the steppings affected, see the

Summary Tables of Changes.

103.

Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue

Problem:

Software which is written so that multiple agents can modify the same shared

unaligned memory location at the same time may experience a memory ordering

issue if multiple loads access this shared data shortly thereafter. Exposure to this

problem requires the use of a data write which spans a cache line boundary.

Implication:

This erratum may cause loads to be observed out of order. Intel has not observed

this erratum with any commercially available software or system.

Workaround:

Software should ensure at least one of the following is true when modifying

shared data by multiple agents:

•

The shared data is aligned.

•

Proper semaphores or barriers are used in order to prevent concurrent data

accesses.

Содержание BX80623I52500K

Страница 1: ...Intel Pentium 4 Processor Specification Update August 2008 Revision 071 Document Number 249199 071...

Страница 2: ...descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definitio...

Страница 3: ...ation Update 3 Contents Preface 9 Summary Tables of Changes 11 General Information 21 Identification Information 24 Errata 31 Specification Changes 69 Specification Clarifications 70 Documentation Cha...

Страница 4: ...pin package Added erratum N48 April 2001 008 Updated the Intel Pentium 4 Processor Identification Information table Added erratum N49 May 2001 009 Updated Specification Update product key to include...

Страница 5: ...have been incorporated into the documentation August 2002 026 Added 2 80 GHz and C1 stepping information August 2002 027 Updated erratum N39 Added Documentation Changes N3 to N24 September 2002 028 Ad...

Страница 6: ...tion Clarification Change N2 Out of Cycle February 2004 046 Added Errata 90 to N92 o N9 and N91 removed in rev049 o N92 changed to N86 Added S Spec number under identification information table March...

Страница 7: ...Cycle November 1 2004 056 Added Erratum N99 Nov 2004 057 Added Erratum N100 December 2004 058 Updated code used in summary table and updated processor identification table February 2005 059 Added Spe...

Страница 8: ...8 Specification Update Revision Description Date 069 Updated Summary Table of Changes May 2007 070 Updated Summary Table of Changes April 2008 071 Updated Summary Table of Changes August 2008...

Страница 9: ...um 4 Processor in the 478 pin Package datasheet 249887 003 http developer intel com d esign pentium4 datashts 24 9887 htm Intel Pentium 4 Processor with 512 KB L2 Cache on 0 13 Micron Process and Inte...

Страница 10: ...o the current published specifications These changes will be incorporated in the next release of the specifications Specification Clarifications describe a specification in greater detail or further h...

Страница 11: ...o this stepping No mark or Blank Box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Status Doc Document change or update that will be implemented Pl...

Страница 12: ...ssor MP with up to 8MB L3 cache V Mobile Intel Celeron processor on 13 micron process in Micro FCPGA package W Intel Celeron M processor X Intel Pentium M processor on 90nm process with 2 MB L2 cache...

Страница 13: ...l Core 2 Extreme processor QX9650 and Intel Core 2 Quad processor Q9000 series AW Intel Core 2 Duo processor E8000 series AX Quad Core Intel Xeon processor 5400 series AY Dual Core Intel Xeon processo...

Страница 14: ...10 X Fixed IERR may not go active when an internal error occurs N11 X Fixed All L2 cache uncorrectable errors are logged as data writes N12 X X X X X X X X No Fix When in no fill mode the memory type...

Страница 15: ...N28 X Fixed Incorrect address for an L1 tag parity error is logged in IA32_MC1_ADDR register N29 X X Fixed REP MOV instruction with overlapping source and destination may result in data corruption N3...

Страница 16: ...e livelock N46 X X Fixed PAT index MSB may be calculated incorrectly N47 X X X Fixed SQRTPD and SQRTSD may return QNaN indefinite instead of negative zero N48 X X X X Fixed Bus invalidate line request...

Страница 17: ...e address as an outstanding Bus Read Line BRL or Bus Read Invalidate Line BRIL N62 X X X X X Fixed L2 cache may contain stale data in the Exclusive state N63 X X X X X X Fixed Re mapping the APIC base...

Страница 18: ...SS May be Incorrect N78 X X X X X X X X No Fix Processor Provides a 4 Byte Store Unlock After an 8 Byte Load Lock N79 X X1 X1 Plan Fix Simultaneous Page Faults at Similar Page Offsets on Both Logical...

Страница 19: ...Last Exception Record MSRs LERs N94 X X X X X X X X No Fix Stores to Page Tables May Not Be Visible to Pagewalks for Subsequent Loads Without Serializing or Invalidating the Page Table Entry N95 X X P...

Страница 20: ...ry Ordering Issue N104 X X X X X X X X No Fix Debug Status Register DR6 Breakpoint Condition Detected Flags May be set Incorrectly NOTE 1 For these steppings this erratum may be worked around in BIOS...

Страница 21: ...y 2 D Matrix Mark FPO Serial Figure 2 Intel Pentium 4 Processor in the 478 Pin Package Markings Example 1 2 GHZ 256 400 1 75V SYYYY XXXXXX FFFFFFFF NNNN i 01 Frequency Cache Bus Voltage S Spec Country...

Страница 22: ...2 40 GHZ 512 800 1 50V SYYYY XXXXXX FFFFFFFF NNNN m c 01 PENTIUM 4 INTEL Frequency Cache Bus Voltage S Spec Country of Assy FPO Serial Figure 5 Multiple VIDs Example 1 2 D Matrix Mark 2 40 GHZ 512 800...

Страница 23: ...ntel Pentium 4 Extreme Edition on 0 13 micron in the 775 Land LGA Package Marking 2 D Matrix Mark 3 40 GHZ 512 800 SYYYY XXXXXX FFFFFFFF PENTIUM 4 INTEL Frequency L2 Cache Bus S Spec Country of Assy F...

Страница 24: ...ecuted with a 1 in the EAX register Table 1 Intel Pentium 4 Processor Identification Information S Spec Core Stepping L2 Cache Size bytes CPUID Speed Core Bus Package and Revision Notes SL4QD B2 256K...

Страница 25: ...9V C1 256K 0F0Ah 1 50GHz 400MHz 31 0 mm FC rev 1 0 4 SL5US C1 256K 0F0Ah 1 60GHz 400MHz 31 0 mm FC rev 1 0 4 SL59X C1 256K 0F0Ah 1 70GHz 400MHz 31 0 mm FC rev 1 0 4 SL5UT C1 256K 0F0Ah 1 80GHz 400MHz...

Страница 26: ...1 5 SL5ZU B0 512K 0F24h 2 20GHz 400MHz 31 0 mm FC rev 1 0 1 5 SL65R B0 512K 0F24h 2 40GHz 400MHz 31 0 mm FC rev 1 0 2 5 SL67R B0 512K 0F24h 2 40GHz 400MHz 31 0 mm FC rev 1 0 1 5 SL683 B0 512K 0F24h 2...

Страница 27: ...31 0 mm FC rev 1 0 1 3 SL6BC E0 256K 0F13h 1 60GHz 400MHz 31 0 mm FC rev 1 0 1 4 SL679 E0 256K 0F13h 1 60GHz 400MHz 31 0 mm FC rev 1 0 2 4 SL6BD E0 256K 0F13h 1 70GHz 400MHz 31 0 mm FC rev 1 0 1 4 SL...

Страница 28: ...GHz 400MHz 31 0 mm FC rev 1 0 2 5 16 SL6PL D1 512K 0F29h 2 20GHz 400MHz 31 0 mm FC rev 1 0 2 5 16 SL6PK D1 512K 0F29h 2GHz 400MHz 31 0 mm FC rev 1 0 2 5 16 SL6PG D1 512K 0F29h 3 06GHz 533MHz 31 0 mm F...

Страница 29: ...Pentium 4 processors in the 478 pin package 5 These processors are Pentium 4 processors with 512 KB L2 cache on 0 13 micron process 6 These parts have some specifications that differ from those in th...

Страница 30: ...Icc_max 60 5 A TDP 78 0 W Tcase 74 C Isgnt 32 0 A 20 Pentium 4 processor with 512 KB L2 cache on 0 13 micron process M 0 stepping is a unique stepping of Pentium 4 processors The currently shipping Pe...

Страница 31: ...f the processor Workaround If a system implementation must support both SMM and board I O restart the first thing the SMM handler code should do is check for a pending MCE If there is an MCE pending t...

Страница 32: ...Tables of Changes 5 Invalid Opcode 0FFFh Requires a ModRM Byte Problem Some invalid opcodes require a ModRM byte or other following bytes while others do not The invalid opcode 0FFFh did not require a...

Страница 33: ...of Changes 8 FSW May Not Be Completely Restored after Page Fault on FRSTOR or FLDENV Instructions Problem If the FPU operating environment or FPU state operating environment and register stack being...

Страница 34: ...ead operations which hit the L2 cache and receive an uncorrectable error with the bit pattern 0100b indicating a Data Write Operation Implication Data Read operations which cause an uncorrectable erro...

Страница 35: ...cessor to the same physical memory address and the more recent store uses a different logical address to reference the same physical address it is possible that a subsequent load from the same physica...

Страница 36: ...about 4 billion 2 32 less than it should Workaround Since this erratum does not occur if the performance counters are read when running a possible workaround is to read the counter before stopping it...

Страница 37: ...r contains stale information Workaround None identified Status For the steppings affected see the Summary Tables of Changes 21 Processor May Hang on a Correctable Error and Snoop Combination Problem T...

Страница 38: ...ted with this uncorrectable error and is therefore erroneous Implication When this erratum occurs erroneous information is logged in the IA32_MC1_STATUS register Workaround None identified Status For...

Страница 39: ...the split load lock goes out on the system bus The first half of the load completes but the uncorrectable error seen earlier prevents the dispatch of the second half of the split load lock and the pr...

Страница 40: ...RIP signals are specified in the Intel Pentium 4 Processor in the 423 pin Package Datasheet as AGTL buffers The buffers for these signals were instead designed with CMOS buffers Implication It is not...

Страница 41: ...CR3 register is always updated from the new task TSS In the mode C paging once the CR3 is changed the processor will attempt to load the PDPTRs If the CR3 from the target task TSS or task switch handl...

Страница 42: ...ception will not be taken When a data breakpoint is set on the ninth and or tenth byte s of a floating point store using the Extended Real data type and an unmasked floating point exception occurs on...

Страница 43: ...rrectable error and the other 32 byte half of the same fetch from the L2 cache has a correctable error the processor will attempt to correct the correctable error but cannot proceed due to the uncorre...

Страница 44: ...If an uncorrectable error is logged in the error reporting bank and another error occurs the overflow bit will not be set The MCA Error Code field of the IA32_MC0_STATUS register gets written by a di...

Страница 45: ...l specific register MSR is software visible but should only be set for the duration of the PCI initialization sequence It is necessary to re enable the timeout counter by clearing this bit after compl...

Страница 46: ...where an L1 parity error occurs and the address is not available because the linear to physical address translation is not complete or an internal resource conflict has occurred the ADDRESS VALID bit...

Страница 47: ...or stalls trying to fetch the bytes of the faulting floating point instruction and those following it This processor hang is caused by interactions between thermal control circuit and floating point e...

Страница 48: ...is set to 1b It is possible that the PAT upper index bit in the PTE for this 4k page is incorrectly ignored and assumed to be 0b The result is that the memory type in the PAT that should have come fro...

Страница 49: ...load Implication No known commercially available chipsets trigger the failure conditions Workaround The chipset could issue a BIL snoop to the deferred processor to eliminate the failure conditions St...

Страница 50: ...Issues Inconsistent Transaction Size Attributes for Locked Operation Problem When the processor is in the Page Address Extension PAE mode and detects the need to set the Access and or Dirty bits in th...

Страница 51: ...les of Changes 56 Associated Counting Logic Must Be Configured When Using Event Selection Control ESCR MSR Problem ESCR MSRs allow software to select specific events to be counted with each ESCR usual...

Страница 52: ...e value of CR2 and the error code pushed on the stack are reflective of the speculative state Intel has not observed this erratum with commercially available software Implication When this erratum occ...

Страница 53: ...ant Forward progress is the primary requirement Status For the steppings affected see the Summary Tables of Changes 62 L2 Cache May Contain Stale Data in the Exclusive State Problem If a cacheline A i...

Страница 54: ...sue by masking off bit 0 in the EAX register where BIST results are written Status For the steppings affected see the Summary Tables of Changes 65 Processor Does Not Flag GP on Non Zero Write to Certa...

Страница 55: ...ndled in a non synchronized way For example if an instruction that masks the interrupt flag e g CLI is executed soon after an uncacheable write to the Task Priority Register TPR that lowers the APIC p...

Страница 56: ...Changes 71 Parity Error in the L1 Cache May Cause the Processor to Hang Problem If a locked operation accesses a line in the L1 cache that has a parity error it is possible that the processor may han...

Страница 57: ...uitry controlling the movement of data to the data bus pins This may result in system or application hang or may cause incorrect data Implication When this erratum occurs system and or application may...

Страница 58: ...possible for the state of the RF flag in the EFLAGS register image to be incorrect Implication The RF flag is normally used for code breakpoint management during debug of an application It is not typi...

Страница 59: ...ady small possibility of encountering this failure by restarting or retrying the faulting instruction and only terminate the application on a subsequent failure of the same instruction It is possible...

Страница 60: ...ng Technology1 Enabled Processor Problem When a Machine Check Exception MCE occurs due to an internal error both logical processors on a Hyper Threading Technology enabled processor normally vector to...

Страница 61: ...e releasing logical processor is executing instructions that are within the detection range of the self modifying code SMC logic then the processor may be locked in the synchronization loop until the...

Страница 62: ...rror is received on the same internal clock that the error status register is being written due to a previous error bit 6 does not get set and illegal vector errors are not flagged Implication The xAP...

Страница 63: ...exist in the clocking of the instruction decoder unit which leads to a circuit slowdown in the read path from the Instruction Decode PLA circuit This timing marginality may not be visible for some pe...

Страница 64: ...ss Refer to the IA 32 Intel Architecture Software Developer s Manual for the correct way to update page tables Software that conforms to the Software Developer s Manual will operate correctly Implicat...

Страница 65: ...BTS PEBS absolute maximum will also continue past the end of the virtual address space A BTS PEBS record can be written that will wrap at the 4G boundary IA32 or 2 64 boundary EM64T mode and write mem...

Страница 66: ...s invalidating snoop will get a clean snoop result 2 Snoop filtering central agents can a Not use processor originated BWIL or BLW transactions to update their snoop filter information OR b Update th...

Страница 67: ...address has bit 20 set The address references a large page A20M is enabled Implication When A20M is enabled and an address references a large page the resulting translated physical address may be inco...

Страница 68: ...breakpoint condition under certain boundary conditions when either A MOV SS or POP SS instruction is immediately followed by a hardware debugger breakpoint instruction or Any debug register access MOV...

Страница 69: ...the 478 pin Package Datasheet Intel Pentium 4 Processor with 512 KB L2 Cache on 0 13 Micron Process and Intel Pentium 4 Processor Extreme Edition Supporting Hyper Threading Technology Datasheet Intel...

Страница 70: ...hitecture Software Developer s Manual Volume 3 System Programming Guide the Time Stamp Counter definition has been updated to include support for the future processors This change will be incorporated...

Страница 71: ...information The RDTSC instruction reads the time stamp counter and is guaranteed to return a monotonically increasing unique value whenever executed except for a 64 bit counter wraparound Intel guaran...

Страница 72: ...nnot be measured on a logical processor basis Time stamp counter Some processor models permit clock cycles to be measured when the physical processor is not in deep sleep by using the time stamp count...

Страница 73: ...Specification Clarifications Specification Update 73...

Страница 74: ...the 478 pin Package Datasheet Intel Pentium 4 Processor with 512 KB L2 Cache on 0 13 Micron Process and Intel Pentium 4 Processor Extreme Edition Supporting Hyper Threading Technology Datasheet Intel...

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