Errata
52
Specification
Update
57.
IA32_MC0_ADDR and IA32_MC0_MISC Registers Will Contain Invalid
or Stale Data following a Data, Address, or Response Parity Error
Problem:
If the processor experiences a data, address, or response parity error, the ADDRV
and MISCV bits of the IA32_MC0_STATUS register are set, but the IA32_MC0_ADDR
and IA32_MC0_MISC registers are not loaded with data regarding the error.
Implication:
When this erratum occurs, the IA32_MC0_ADDR and IA32_MC0_MISC registers will
contain invalid or stale data.
Workaround:
Ignore any information in the IA32_MC0_ADDR and IA32_MC0_MISC registers
after a data, address or response parity error.
Status:
For the steppings affected, see the
Summary Tables of Changes.
58.
CR2 May Be Incorrect or an Incorrect Page Fault Error Code May Be
Pushed onto Stack after Execution of an LSS Instruction
Problem:
Under certain timing conditions, the internal load of the selector portion of the LSS
instruction may complete with potentially incorrect speculative data before the load of
the offset portion of the address completes. The incorrect data is corrected before the
completion of the LSS instruction but the value of CR2 and the error code pushed on
the stack are reflective of the speculative state. Intel has not observed this erratum
with commercially available software.
Implication:
When this erratum occurs, the contents of CR2 may be off by two, or an incorrect
page fault error code may be pushed onto the stack.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
59.
BPM[5:3]# VIL Does Not Meet Specification
Problem:
The V
IL
for BPM[5:3]# is specified as 0.9 * GTLREF [V]. Due to this erratum the V
IL
for these signals is 0.9 * GTLREF - .100 [V].
Implication:
The processor requires a lower input voltage than specified to recognize a low voltage
on the BPM[5:3]# signals.
Workaround:
When intending to drive the BPM[5:3]# signals a low, ensure that the system
provides a voltage lower than 0.9 * GTLREF - .100 [V].
Status:
For the steppings affected, see the
Summary Tables of Changes.
60.
Processor May Hang under Certain Frequencies and 12.5% STPCLK#
Duty Cycle
Problem:
If a system de-asserts STPCLK# at a 12.5% duty cycle, the processor is running
below 2 GHz, and the processor thermal control circuit (TCC) on-demand clock
modulation is active, the processor may hang. This erratum does not occur under the
automatic mode of the TCC.
Implication:
When this erratum occurs, the processor will hang.
