Intel BX80605X3440 - Quad Core Xeon X3440, Справочник

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Thermal Specifications
48 Document Number: 424077 Revision: 2.0Thermal/Mechanical
Specifications and Design Guidelines
transitioning to the minimum frequency and corresponding voltage (using Freq/VID
control). Clock modulation is not activated in this case. The TCC will remain active until
the system de-asserts PROCHOT#.
Use of PROCHOT# in bi-directional mode can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system
cooling failure. The system thermal design should allow the power delivery circuitry to
operate within its temperature specification even while the processor is operating at its
Thermal Design Power.
6.2.3 THERMTRIP# Signal
Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached an elevated temperature. At this point, the THERMTRIP# signal will go
active and stay active as described in the datasheet. THERMTRIP# activation is
independent of processor activity. The temperature at which THERMTRIP# asserts is
not user configurable and is not software visible.
6.3 Platform Environment Control Interface (PECI)
6.3.1 Introduction
The Platform Environment Control Interface (PECI) is a one-wire interface that provides
a communication channel between Intel processor and chipset components to external
monitoring devices. The processor implements a PECI interface to allow communication
of processor thermal and other information to other devices on the platform. The
processor provides a digital thermal sensor (DTS) for fan speed control. The DTS is
calibrated at the factory to provide a digital representation of relative processor
temperature. Instantaneous temperature readings from the DTS are available using the
IA32_TEMPXXXX MSR; averaged DTS values are read using the PECI interface.
The PECI physical layer is a self-clocked one-wire bus that begins each bit with a
driven, rising edge from an idle level near zero volts. The duration of the signal driven
high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes
variable data transfer rate established with every message. The single wire interface
provides low board routing overhead for the multiple load connections in the congested
routing area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability to transfer
critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 Kbps to 2 Mbps
• CRC check byte used to efficiently and automatically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
accuracy requirements.
Generic PECI specification details are out of the scope of this document. What follows is
a processor-specific PECI client definition, and is largely an addendum to the PECI
Network Layer and Design Recommendations sections for the PECI 2.0 specification
document.
For system temperature monitoring and fan speed control management purposes, the PECI 2.0