Intel ARM Cortex-A9, Руководство по введению

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I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
adds 1 to the contents of R1 and places the sum into R0. The constant
value
can be specified as a decimal number,
as in this example, or as a binary value #0b1, or as a hexadecimal value #0x1. Valid constants include any eight-bit
value, such as 0xFF. The eight-bit value can also be produced by rotation in a 32-bit word—for example, other valid
constants include 0xFF000000, 0xFF0000, and 0xFF00. In general, the constant can be any value which can be
generated by rotating a byte to the right any
even number of times (0, 2, . . . , 30) in a 32-bit word (see the ARM
Assembler Reference for more details).
Alternatively, Operand2 can be given as a register R m , as in
OP R d , R n , R m
This instruction performs the operation OP using the contents of R
n
and R
m
, and places the result into R
d
. For
example
ADD R0, R1, R2
adds the contents of R1 and R2, and places the sum into R0.
When Operand2 is a register, R m can either be used directly, as in the above example, or else its value can be shifted
before being used. If it is shifted, then the shifting amount can be specified as a five-bit constant, as in
OP R d , R n , R m , LSL #3
or as the least-significant byte of a register R s , as in
OP R d , R n , R m , LSL R s
In these examples LSL means Logical Shift Left . Other examples of shift variants include right-shift, and rotate
operations, as discussed in section 6.7 .
6.3.1 Using Condition Code Flags
The data processing instructions can optionally affect the ARM condition code flags, or can be executed conditionally
based on the values of the condition code flags. These options are expressed in the general form
OP{S}{cond} R d , R n ,
Operand2
If S is included in the instruction mnemonic, as in ADDS, then the condition code flags will be set depending on the
results of the instruction. But if
S
is not included, as in ADD, then the flags are unaffected by the instruction. Setting
of the condition code flags is discussed further in Section 6.9 .
An optional cond appended to an instruction mnemonic allows an instruction to be either executed or skipped,
depending on the current values of the condition code flags. This concept is discussed in Section 6.10 .
10 Intel Corporation - FPGA University Program
November 2016