I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
a 32-bit address that denotes the location AVECTOR is loaded into register R0, as explained in Section
6.6.1
But, in
the instruction
LDR
R2, N
it is the value 6, which is stored at location N, that is loaded into register R2. In both cases, the assembled LDR
machine instruction will use Relative addressing to access the source operand.
9
Operating Modes
The ARM processor can operate in a number of different modes, as follows:
•
User
mode – is the basic mode in which application programs run. This is an unprivileged mode, which has
restricted access to system resources.
•
System
mode – provides full access to system resources. It can be entered only from one of the exception
modes listed below.
•
Supervisor
mode – is entered when a software interrupt is raised by a program executing a Supervisor Call
instruction, SVC. It is also entered on reset or power-up.
•
Abort
mode – is entered if a program attempts to access a non-existing memory location.
•
Undefined
mode – is entered if the processor attempts to execute an unimplemented instruction.
•
IRQ
mode – is entered in response to a normal interrupt request from an external device.
•
FIQ
mode – is entered in response to a
fast interrupt
request from an external device. It is used to provide
faster service for more urgent requests.
The User mode is unprivileged, and all other modes are privileged. In order to manipulate the contents of the
processor status register, the processor must be in one of the privileged modes. The User and System modes use
the registers presented in Figure 1. Other modes, which deal with various exceptions, use some other registers, as
described in the next section.
The current operating mode is indicated in the processor status bits CPSR
4
−
0
, as specified in Table 3.
20
Intel Corporation - FPGA University Program
November 2016
