I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
31
0
28
Condition
27
11
20 19
16 15
12
OP code
Rn
Rd
Offset or Rm
Figure 2. Format for Load and Store instructions.
6
ARM Instructions
ARM instructions are 32-bits long. In addition to machine instructions that are executed directly by the processor,
the ARM instruction set includes a number of
pseudo-instructions
that can be used in assembly language programs.
The Assembler replaces each pseudo-instruction by one or more machine instructions.
This section discusses briefly the main features of the ARM instruction set. For a complete description of the instruc-
tion set, including the details of how each instruction is encoded, the reader should consult the
ARM Architecture
Reference Manual
.
6.1
Load and Store Instructions
Load and store instructions are used to move data between memory (and I/0 interfaces) and the general-purpose
registers. The LDR (Load Register) instruction, illustrated in the previous section, loads a 32-bit operand into a
register. The corresponding
Store
instruction is STR (Store Register). For example,
STR R2, [R4]
copies the contents of R2 into memory location at the address that is found in register R4.
There are also load and store instructions that use operands that are only 8 or 16 bits long. They are referred to as
Load/Store Byte and Load/Store Halfword instructions, respectively. Such load instructions are:
• LDRB (Load Register Byte)
• LDRSB (Load Register Signed Byte)
• LDRH (Load Register Halfword)
• LDRSH (Load Register Signed Halfword)
When a shorter operand is loaded into a 32-bit register, its value has to be adjusted to fit into the register. This is
done by zero-extending the 8- or 16-bit value to 32 bits in the LDRB and LDRH instructions. In the LDRSB and
LDRSH instructions the operand is sign-extended.
The corresponding
Store
instructions are:
• STRB (Store Register Byte)
Intel Corporation - FPGA University Program
November 2016
7
