Intel ARM Cortex-A9, Руководство по введению

Страница: 9 / 29

I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
The LDM and STM instructions are very useful in the context of subroutines, where they can be used to save
the contents of registers on the stack. For this purpose, there exist pseudo-instructions PUSH and POP, which are
actually implemented as particular forms of STM and LDM instructions. In these instructions the Stack Pointer, SP,
is the base register, which is always updated. The SP is decremented by 4 before each transfer in PUSH instructions,
and it is incremented by 4 after each transfer in POP instructions. For example, the instruction
PUSH {R1, R3
−
R5}
places the contents of registers R5, R4, R3 and R1 onto the stack. The equivalent
Store Multiple
instruction is
STMDB SP!, {R1, R3 − R5}
The instruction
POP {R1, R3 − R5}
restores the contents of these registers from the stack. The equivalent Load Multiple instruction would be
LDMIA SP!, {R1, R3
−
R5}
6.2 Data Processing Instructions
A variety of ARM instructions are provided for the processing of data, including instructions that perform shifting,
arithmetic operations, logical operations, and data transfer between registers.
6.3 Flexible Operands
A number of data processing instruction have the general form
OP R d , R n , Operand2
where R d is the destination register, R n is the first operand, and Operand2 is the second operand. A considerable
amount of flexibility is provided by Operand2 . It can be an immediate constant, as in
OP R d , R n , #value
This instruction performs the operation
OP
using the contents of R n and the constant
value
, and places the result
into R d . For example, if OP is the addition instruction ADD, then
ADD R0, R1, #1
Intel Corporation - FPGA University Program
November 2016
9