I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
Observe that 0x000 is inserted in address location 0x014, because this vector location is not allocated to servicing an
exception. Observe also that the return from the exception-service routines used as an example is done as explained
in sections
11.2
and
11.2.1
.
12
Input/Output Operations
Most I/O devices are accessed by means of their memory-mapped registers. When a program accesses such devices,
it is important that each access is made to an actual register. In a processor with a data cache, it is essential to ensure
that the cached data is not used instead of the current values in the I/O device registers. In effect, the data cache
has to be bypassed when reading or writing the registers in I/O devices. The ARM processor does not have separate
instructions for reading and writing the contents of I/O registers. Instead, all I/O devices must have their registers
mapped into a memory address region that will not be cached by the processor. This can be accomplished if the
processor data cache is disabled completely, or if the processor’s memory management unit (MMU) is set up such
that appropriate regions of memory are designated as non-cacheable. The procedure for setting up the MMU and
data cache is beyond the scope of this document.
28
Intel Corporation - FPGA University Program
November 2016
