I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
5
Accessing Memory and I/O Devices
Any input/output devices that can be accessed by the ARM processor are memory mapped and can be accessed
as memory locations. Data accesses to memory locations and I/O interfaces are performed by means of Load and
Store instructions, which cause data to be transferred between the memory and general-purpose registers. The ARM
processor issues 32-bit addresses. The memory space is byte-addressable. Instructions can read and write
words
(32
bits),
halfwords
(16 bits), or
bytes
(8 bits) of data.
5.1
Addressing Modes for Load and Store Instructions
The Load and Store instructions are the only type of instructions that can access memory locations. Load instructions
copy the contents of a memory location specified by an addressing mode into a destination register, which is a
general-purpose register, R
d
. Store instructions copy the contents of a general-purpose register, R
d
, into a memory
location specified by an addressing mode.
An addressing mode provides the information needed to determine the address of the desired memory location.
There are different ways of specifying the required address. All addressing modes involve one or two general-
purpose registers, plus some additional information. One register is referred to as the
base
register, R
n
. If a second
register is used, it is referred to as the
index
register, R
m
. The memory address is determined by adding the contents
of the base register and a value that is either given as a signed 12-bit
offset
directly in the instruction or as a magnitude
in the index register. The magnitude in R
m
can be scaled by shifting it either left or right a number of bit-positions
specified in the instruction.
There are three primary addressing modes provided:
•
Offset
mode – the address is determined by adding the contents of a base register and an offset that is either
given directly in the instruction or in an index register.
•
Pre-indexed
mode – the address is determined in the same way as in the Offset mode; subsequently, this
address replaces the contents of the base register used.
•
Post-indexed
mode – the address is the contents of a base register; subsequently, the base register is loaded
with a new address that is determined in the same way as in the Offset mode.
These addressing modes are fully specified in Table 1, which indicates how the address generation is performed.
The table also gives the required Assembler syntax.
When an index register is specified, its contents are interpreted as a magnitude which can be either added to or
subtracted from a base register. This magnitude can first be shifted left or right by specifying LSL #k or LSR #k,
respectively, where k is an integer from 1 to 31. Shifting operations are discussed further in section
6.7
.
Since the Program Counter, R15, can be treated as a general-purpose register, it can be used in the Offset addressing
mode as a base register, R
n
. This makes it possible to access memory locations in terms of their distance relative to
the current address in R15. This mode is often referred to as the
Relative
addressing mode.
4
Intel Corporation - FPGA University Program
November 2016