Intel 8XC251SA, Руководство пользователя

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5-5
PROGRAMMING
5.3.1.1 Register Addressing
Both architectures address registers directly.
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MCS 251 architecture. In the register addressing mode, the operand(s) in a data instruction
are in byte registers (R0–R15), word registers (WR0, WR2, ..., WR30), or dword registers
(DR0, DR4, ..., DR28, DR56, DR60).
•
MCS 51 architecture. Instructions address registers R0–R7 only.
5.3.1.2 Immediate
Both architectures use immediate addressing.
•
MCS 251 architecture. In the immediate addressing mode, the instruction contains the data
operand itself. Byte operations use 8-bit immediate data (#data); word operations use 16-bit
immediate data (#data16). Dword operations use 16-bit immediate data in the lower word,
and either zeros in the upper word (denoted by #0data16), or ones in the upper word
(denoted by #1data16). MOV instructions that place 16-bit immediate data into a dword
register (DRk), place the data either into the upper word while leaving the lower word
unchanged, or into the lower word with a sign extension or a zero extension.
The increment and decrement instructions contain immediate data (#short = 1, 2, or 4) that
specifies the amount of the increment/decrement.
•
MCS 51 architecture. Instructions use only 8-bit immediate data (#data).
5.3.1.3 Direct
•
MCS 251 architecture. In the direct addressing mode, the instruction contains the address of
the data operand. The 8-bit direct mode addresses on-chip RAM (dir8 = 00:0000H–
00:007FH) as both bytes and words, and addresses the SFRs (dir8 = S:080H–S:1FFH) as
bytes only. (See the notes in section 5.3.1, “Data Addressing Modes,” regarding SFRs in the
MCS 251 architecture.) The 16-bit direct mode addresses both bytes and words in memory
(dir16 = 00:0000H–00:FFFFH).
•
MCS 51 architecture. The 8-bit direct mode addresses 256 bytes of on-chip RAM (dir8 =
00H–7FH) as bytes only and the SFRs (dir8 = 80H–FFH) as bytes only.