Intel 8XC251SA, Руководство пользователя

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8XC251SA, SB, SP, SQ USER’S MANUAL
9-14
Figure 9-8. CCON: PCA Timer/Counter Control Register
CCON
Address: S:D8H
Reset State: 00X0 0000B
7 0
CF CR — CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number
Bit
Mnemonic
Function
7 CF PCA Timer/Counter Overflow Flag:
Set by hardware when the PCA timer/counter rolls over. This generates
an interrupt request if the ECF interrupt enable bit in CMOD is set. CF
can be set by hardware or software but can be cleared only by software.
6 CR PCA Timer/Counter Run Control Bit:
Set and cleared by software to turn the PCA timer/counter on and off.
5 — Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
4:0 CCF4:0 PCA Module Compare/Capture Flags:
Set by hardware when a match or capture occurs. This generates a PCA
interrupt request if the ECCF
x interrupt enable bit in the corresponding
CCAPM x register is set. Must be cleared by software.
Table 9-3. PCA Module Modes
ECOM
x
CAPP
x
CAPN
x
MAT
x
TOG
x
PWM
x
ECCF
x
Module Mode
0 0 0 0 0 0 0 No operation
X 1 0 0 0 0 X 16-bit capture on positive-edge
trigger at CEX
x
X 0 1 0 0 0 X 16-bit capture on negative-edge
trigger at CEX
x
X 1 1 0 0 0 X 16-bit capture on positive- or
negative-edge trigger at CEX
x
1 0 0 1 0 0 X Compare: software timer
1 0 0 1 1 0 X Compare: high-speed output
1 0 0 0 0 1 0 Compare: 8-bit PWM
1 0 0 1 X 0 X Compare: PCA WDT
(CCAPM4 only) (Note 3)
NOTES:
1.
This table shows the CCAPM x register bit combinations for selecting the operating modes of the PCA
compare/capture modules. Other bit combinations are invalid. See Figure 9-9 for bit definitions.
2. x = 0–4, X = Don’t care.
3. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.