11-13
MATH COPROCESSING
11.4.4 Exception Trapping
The 80C187 detects six error conditions that can occur during instruction execution. The 80C187
can apply default fix-ups or signal exceptions to the microprocessor’s ERROR pin. The processor
tests ERROR at the beginning of numerics instructions, so it traps an exception on the next at-
tempted numerics instruction after it occurs. When ERROR tests active, the processor executes a
Type 16 interrupt.
There is no automatic exception-trapping on the last numerics instruction of a series. If the last
numerics instruction writes an invalid result to memory, subsequent non-numerics instructions
can use that result as if it is valid, further compounding the original error. Insert the FNOP in-
struction at the end of the 80C187 routine to force an ERROR check. If the program is written in
a high-level language, it is impossible to insert FNOP. In this case, route the error signal through
an inverter to an interrupt pin on the microprocessor (see Figure 11-4). With this arrangement,
use a flip-flop to latch BUSY upon assertion of ERROR. The latch gets cleared during the excep-
tion-handler routine. Use an additional flip-flop to latch PEREQ to maintain the correct hand-
shaking sequence with the microprocessor.
11.5 EXAMPLE MATH COPROCESSOR ROUTINES
Example 11-1 shows the initialization sequence for the 80C187. Example 11-2 is an example of
a floating point routine using the 80C187. The FSINCOS instruction yields both sine and cosine
in one operation.
Содержание 80C186XL
Страница 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Страница 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Страница 18: ...1 Introduction...
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Страница 28: ...2 Overview of the 80C186 Family Architecture...
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Страница 80: ...3 Bus Interface Unit...
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Страница 128: ...4 Peripheral Control Block...
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Страница 138: ...5 ClockGenerationand Power Management...
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Страница 154: ...6 Chip Select Unit...
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Страница 178: ...7 Refresh Control Unit...
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Страница 194: ...8 Interrupt Control Unit...
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Страница 228: ...9 Timer Counter Unit...
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Страница 254: ...10 Direct Memory Access Unit...
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Страница 284: ...11 Math Coprocessing...
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Страница 302: ...12 ONCE Mode...
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Страница 306: ...A 80C186 Instruction Set Additions and Extensions...
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Страница 318: ...B Input Synchronization...
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Страница 322: ...C Instruction Set Descriptions...
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Страница 372: ...D Instruction Set Opcodes and Clock Cycles...
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Страница 396: ...Index...
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