CONTENTS
xii
FIGURES
Figure
Page
6-11
Wait State and Ready Control Functions ...................................................................6-16
6-12
Using Chip-Selects During HOLD ..............................................................................6-18
6-13
Typical System ...........................................................................................................6-19
7-1
Refresh Control Unit Block Diagram.............................................................................7-1
7-2
Refresh Control Unit Operation Flow Chart..................................................................7-3
7-3
Refresh Address Formation..........................................................................................7-4
7-4
Suggested DRAM Control Signal Timing Relationships...............................................7-6
7-5
Formula for Calculating Refresh Interval for RFTIME Register ....................................7-7
7-6
Refresh Base Address Register ...................................................................................7-8
7-7
Refresh Clock Interval Register....................................................................................7-9
7-8
Refresh Control Register ............................................................................................7-10
7-9
Regaining Bus Control to Run a DRAM Refresh Bus Cycle.......................................7-13
8-1
Interrupt Control Unit in Master Mode ..........................................................................8-2
8-2
Using External 8259A Modules in Cascade Mode .......................................................8-8
8-3
Interrupt Control Unit Latency and Response Time ...................................................8-11
8-4
Interrupt Control Register for Internal Sources...........................................................8-13
8-5
Interrupt Control Register for Noncascadable External Pins ......................................8-14
8-6
Interrupt Control Register for Cascadable Interrupt Pins............................................8-15
8-7
Interrupt Request Register .........................................................................................8-16
8-8
Interrupt Mask Register ..............................................................................................8-17
8-9
Priority Mask Register ................................................................................................8-18
8-10
In-Service Register .....................................................................................................8-19
8-11
Poll Register ...............................................................................................................8-20
8-12
Poll Status Register ....................................................................................................8-21
8-13
End-of-Interrupt Register ............................................................................................8-22
8-14
Interrupt Status Register ............................................................................................8-23
8-15
Interrupt Control Unit in Slave Mode ..........................................................................8-24
8-16
Interrupt Sources in Slave Mode ................................................................................8-25
8-17
Interrupt Vector Register (Slave Mode Only)..............................................................8-27
8-18
End-of-Interrupt Register in Slave Mode ....................................................................8-28
8-19
Request, Mask, and In-Service Registers ..................................................................8-28
8-20
Interrupt Vectoring in Slave Mode ..............................................................................8-29
8-21
Interrupt Response Time in Slave Mode ....................................................................8-30
9-1
Timer/Counter Unit Block Diagram...............................................................................9-2
9-2
Counter Element Multiplexing and Timer Input Synchronization..................................9-3
9-3
Timers 0 and 1 Flow Chart ...........................................................................................9-4
9-4
Timer/Counter Unit Output Modes................................................................................9-6
9-5
Timer 0 and Timer 1 Control Registers ........................................................................9-7
9-6
Timer 2 Control Register ..............................................................................................9-9
9-7
Timer Count Registers................................................................................................9-10
9-8
Timer Maxcount Compare Registers..........................................................................9-11
9-9
TxOUT Signal Timing .................................................................................................9-15
10-1
Typical DMA Transfer.................................................................................................10-2
10-2
DMA Request Minimum Response Time ...................................................................10-4
Содержание 80C186XL
Страница 1: ...80C186XL 80C188XL Microprocessor User s Manual...
Страница 2: ...80C186XL 80C188XL Microprocessor User s Manual 1995...
Страница 18: ...1 Introduction...
Страница 19: ......
Страница 27: ......
Страница 28: ...2 Overview of the 80C186 Family Architecture...
Страница 29: ......
Страница 79: ......
Страница 80: ...3 Bus Interface Unit...
Страница 81: ......
Страница 127: ......
Страница 128: ...4 Peripheral Control Block...
Страница 129: ......
Страница 137: ......
Страница 138: ...5 ClockGenerationand Power Management...
Страница 139: ......
Страница 154: ...6 Chip Select Unit...
Страница 155: ......
Страница 178: ...7 Refresh Control Unit...
Страница 179: ......
Страница 193: ......
Страница 194: ...8 Interrupt Control Unit...
Страница 195: ......
Страница 227: ......
Страница 228: ...9 Timer Counter Unit...
Страница 229: ......
Страница 253: ......
Страница 254: ...10 Direct Memory Access Unit...
Страница 255: ......
Страница 283: ......
Страница 284: ...11 Math Coprocessing...
Страница 285: ......
Страница 302: ...12 ONCE Mode...
Страница 303: ......
Страница 306: ...A 80C186 Instruction Set Additions and Extensions...
Страница 307: ......
Страница 318: ...B Input Synchronization...
Страница 319: ......
Страница 322: ...C Instruction Set Descriptions...
Страница 323: ......
Страница 371: ......
Страница 372: ...D Instruction Set Opcodes and Clock Cycles...
Страница 373: ......
Страница 396: ...Index...
Страница 397: ......