Integra DTR-7.6 Series, Руководство по обслуживанию

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DTR-7.6
IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183 (Advanced Video Decoder with 10-Bit ADC and Component Support)
BLOCK DIAGRAM
ISO
REFOUT
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
ANALOG I/P
MULTIPLEXING
CLAMP AND
DC RESTRE
10-BIT
ADC
LUMA
ANTIALIAS
LPF
SHAPING
AND
NOTCH LPF
PEAKING
HPF/LPF
CHROMA
COMB
FILTER
SYNC
DETECTION
ADV7183
SHAPING
LPF
SWITCH
2H LINE
MEMORY
SUB-
CARRIER
RECOVERY
DTO
10-BIT
ADC
27MHz
27MHz XTAL
OSCILLATOR
BLOCK
HSYNC FIELD VSYNC HREF VREF CLOCK
AFF
HFF/QCLK
AEF
DV
RD
LLC
SYNTHESIS
WITH LINE-
LOCKED
OUTPUT
CLOCK
I2 C-COMPATIBLE
INTERFACE PORT
SCLOCK RESET ALSB
GL/CLKIN
LLC1
LLC2
LLCREF
ELPF
P15-P0
PIXEL
O/P POR T
AUTOMATIC
GAIN
CONTROL
(AGC)
VIDEO TIMING AND
CONTROL BLOCK
FIFO CONTROL
BLOCK
AND
PIXEL
OUTPUT
FORMATTER
LUMA
DELAY
BLOCK
RESAMPLING
AND
HORIZONTAL
SCALING
SDATA PWRDN
RESAMPLING
AND
HORIZONTAL
SCALING
CHROMA
ANTIALIAS
LPF
OE
CLOCK
TERMINAL DESCRIPTION
Pin Mnemonic Input/Output Function
1 VS/VACTIVE O VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
2 HS/HACTIVE O
3, 14 DVSSIO G Digital I/O Ground
4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V)
5-8, 19-24, P15-P0 O Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15-P8),
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
32, 33, 73-76
9, 31, 71 DVSS1-3 G Ground for Digital Supply
10, 30, 72 DVDD1-3 P Digital Supply Voltage (3.3 V)
11 AFF O Almost Full Flag. A FIFO control signal indicating when the FIFO has
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
12 HFF/QCLK/GL I/O Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
13 AEF O Almost Empty Flag. A FIFO control signal, it indicates when the FIFO
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
16 CLKIN I Asynchronous FIFO Clock. This asynchronous clock is used to output
data onto the P19-P0 bus and other control signals.
17, 18, 34, 35 GPO[3:0] O General-Purpose Outputs controlled via I C
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
2