Integra DTR-7.6 Series, Руководство по обслуживанию

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DTR-7.6
CS494003(Audio Decoder DSP)
IC BLOCK DIAGRAMS AND DESCRIPTIONS
PIN NO.
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LRCLK0:Audio Output Sample Rate Clock
AUDATA2:PCM digital-audio data output.
AUDATA3, XMT958A:Digital Audio Output 3, S/PDIF Transmitter
HDATA3, GPIO3:DSPC Bidirectional Data Bus, General Purpose I/O
SCLK0
HDATA4, GPIO4:DSPC Bidirectional Data Bus, General Purpose I/O
AUDATA4, GPIO28:Digital Audio Output 4, General Purpose I/O.PCM digital-audio data output.
VSS2:2.5V ground.
VDD2:2.5V supply voltage.
MCLK:Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.
SCLK1
HDATA5, GPIO5:DSPC Bidirectional Data Bus, General Purpose I/O
AUDATA1:PCM digital-audio data output.
AUDATA0:PCM digital-audio data output.
CMPCLK, FSCLKN2:PCM Audio Input Bit Clock:Digital- audio bit clock input.
HDATA2, GPIO2:DSPC Bidirectional Data Bus, General Purpose I/O
VSS3:2.5V ground.
VDD3:2.5V supply voltage.
HDATA1, GPIO1:DSPC Bidirectional Data Bus, General Purpose I/O
HDATA0, GPIO0:DSPC Bidirectional Data Bus, General Purpose I/O
CMPREQ, FLRCLKN2:PCM audio input request
CMPDAT, FSDATAN2:Digital-audio data input that can accept either one compressed line or 2 channels of PCM data.
FLRCLKN1:Digital-audio frame clock input.
WR, DS, GPIO10:Host Write Strobe, Host Data Strobe, General Purpose I/O
RD, R/W, GPIO11:Host Parallel Output Enable, Host Parallel R/W, General Purpose I/O
PLLVSS :PLL Ground Voltage
FILT2:
FILT1:
PLLVDD:2.5V PLL supply voltage.
XTALO:
CLKIN, XTALI:External Clock input / Crystal Oscillator input:12MHz crystal oscillator is connected.
CLKSEL:DSP Clock select input
CS, GPIO9:Host Parallel Chip Select, General Purpose I/O
A0, GPIO13:Host Address Bit 0, General Purpose I/O
FSDATAN1:Digital-audio data input can accept from one compressed line or 2 channels of PCM data.
VDD4:2.5V supply voltage.
VSS4:2.5V ground.
FSCLKN1, STCCLK2:Digital audio bit clock input.
SCS:Host Serial SPI Chip Select:SPI mode active-low chip-select input signal.
SCDIN:SPI Serial Control Data Input:In SPI mode this pin serves as the data input pin.
VSS5:2.5V ground.
VDD5:2.5V supply voltage.
A1, GPIO12:Host Address Bit 1, General Purpose I/O
SCDOUT, SCDIO:Serial Control Port Data Input and Output:In SPI mode this pin serves as the data output pin.
HINBSY, GPIO8:
SCCLK
UHS2, CS_OUT, GPIO17:Mode Select Bit 2, External Serial Memory Chip Select,General Purpose I/O
RESET :Master Reset Input:Asynchronous active-low master reset input.
TERMINAL NAME/DESCIPTION
Phase-Locked Loop Filter. Connects to an external filter for the phase-locked loop.
Crystal oscillator output.
Phase-Locked Loop Filter. Connects to an external filter for the phase-locked loop.
Input host Message Status, General Purpose I/O. This pin is indicates that serial
:This pin serves as the serial SPI clock input.
:Audio Output Bit Clock:Bidirectional digital-audio output bit clock for AUDATA0, to AUDATA3.
:Audio Output Bit Clock:Bidirectional digital-audio output bit clock for AUDATA4, to AUDATA7.
or parallel communication data written to the DSP has not been read yet.
As an output, SCLK1 can provide 32 fs, 64 fs, 128 fs, 256 fs, or 512 fs frequencies and is synchronous to MCLK.