Firmware User Manual (AE-step)
39
Revision 1.02
2019-04-24
TLE984x Firmware User Manual
Padding Bytes
For FastLIN:
If the customer adds padding bytes, although this is not regular it is still supported by the firmware. Padding
bytes up to a data field size of 128 bytes are possible. The firmware will accept the real data and will find the
checksum byte after the last padding byte.
RAM Access Limitation
Access to the BootROM RAM is limited for the BSL commands
and
Command 02H – RAM: Write Data/Program
. In all boot modes, the full RAM range can be read but global
variables/data and stack area cannot be written to. Trying to write to these areas will result in an error.
RAM and NVM Address Range Checks
All commands reading or writing the NVM or RAM check the address range and return an error if it is exceeded.
The number of bytes to be read or written must be greater than zero.
Blocking of BSL commands due to NVM protection
With any command, the BSL applies checks to determine if the command can get executed. BSL commands
accessing the NVM also check the applied read or write NVM HW protection scheme against the NVM access
request. Details are given specifically with each BSL command description. An errror is returned upon any
access violation.
states which NVM protection group is checked before a given BSL command is
executed.
Definitions of NVM protection groups:
•
Group 1
= NVM HW read or write protection applied to any NVM region. Reason for this: BSL download is
blocked in case any protection is set. This is done to avoid BSL download of code into any region (even
100TP pages).
•
Group 2
= NVM HW read protection applied to any NVM region. Reason for this: BSL download is blocked
in case any protection is set. This is done to avoid BSL download of code into any region (even 100TP
pages).
•
Group 3
= NVM HW read protection applied to any NVM region and no write protection to NVM code region.
Reason for this: When in user mode, instead, the concept is that for CS accessible page (e.g. 100TP pages)
the FW should apply the same protection set for the user code region. This means that the 100TP write via
User API should be blocked only in case the write protection of the code region (checked by looking at the
NVM_PROT_STS bits) is set.
•
Group 4
= NVM HW read and write protection for all regions are ignored. Reason for this: For a command
that can change protection, must be allowed access independently of protection.
