Firmware User Manual (AE-step)
113
Revision 1.02
2019-04-24
TLE984x Firmware User Manual
Appendix E – Device settings in NVM CS
The BootROM uses pre-configured settings written to NVM CS, which all are used to perform various tasks
inside the device. This section show the settings used for different modules.
Table 6-11 BSL module configuration
NVM CS entry
Value
Description
CS_CUST_BSLSIZE
0x00
Size definition of Customer BSL region. 0x00 = CBSL
Size is 4K, 0x01 = CBSL Size is 8K, 0x02 = CBSL Size is
12K, 0x03 = CBSL Size is 16K
CS_NVM_BSL_INTERFACE
0x01
BSL Interface Selection. 0x00 = LIN, 0x01 =FastLIN
CS_NVM_BSL_NAD
0xFF
BSL LIN NAD value
CS_NVM_BSL_INTERFRAME_TO 0x0038
BSL FastLIN and LIN interface timeout. 1 step is 5ms.
CS_NVM_BSL_NAC
0xFF
BSL NAC value. 1 step is 5ms up to 140ms.
0xFF: no timeout used, wait forever
Table 6-12 Startup module configuration
NVM CS entry
Value
Description
CS_SCU_APCLK_CFG
0x02000B00 or
0x02001301
PLL divider settings , depends on device variant:
0x02000B00 (25 MHz), 0x02001301 (40 MHz)
Analog Module Clock Factor (APCLK1FAC)[1:0] 0x00
= divide by 1, 0x01 = divide by 2, 0x02 = divide by 3,
0x03 = divide by 4
Slow Down Clock Divider for TFILT_CLK Generation
(APCLK2FAC) [12:8] 0x01 = fsys/2 to 0x12 = fsys/12,
0x1E = fsys/31, 0x1F = fsys/32
Bandgap Clock Selection (BGCLK_SEL)[24] 0 =
LP_CLK is selected, 1 = fsys is selected
Bandgap Clock Divider (BGCLK_DIV)[25] 0= divide
by 2, 1 = divide by 1
CS_SCU_PLL_DIVIDER_CFG
0x006E or 0x004A
PLL divider settings , depends on device variant:
0x6E (25 MHz), 0x4A (40 MHz)
PLL PDIV-Divider [7:6] = Register
SCU_CMCON1.PDIV
0x00: 4, 0x01: 5, 0x02: 6, 0x03: 6
PLL K2-Divider [5:4] = Register SCU_CMCON1.K2DIV
0x00 K2 = 2, 0x01 K2 = 3, 0x02 K2 = 4, 0x03 K2 = 5
PLL N-Divider [3:0] = Register SCU_PLL_CON.NDIV
0x00 N = 48, 0x01 N = 50, 0x02 N = 51, 0x03 N = 52,
0x04 N = 54, 0x05 N = 60, 0x06 N = 67
CS_NVM_RAM_MBIST
0x0000
RAM test (MBIST) performed during bootup besides
POR. 0 = disabled, 1 = enabled.