IEI Technology IMBA-8654, Руководство пользователя

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IMBA-8654 Motherboard
Page 13
Host Interface Support
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Intel® Pentium® 4 processors with 512-KB L2 cache on 0.13 micron
process / Pentium 4 processor on 90 nm process
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64-bit FSB frequencies of 400 MHz (100 MHz bus clock), 533 MHz (133
MHz bus clock), and 800 MHz (200 MHz bus clock). Maximum theoretical
BW of 6.4 GB/s.
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FSB Dynamic Bus Inversion on the data bus
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32-bit addressing for access to 4 GB of memory space
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Hyper-Threading Technology
System Memory Controller Support
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Dual-channel (128 bits wide) DDR memory interface
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Single-channel (64 bits wide) DDR operation supported
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Symmetric and asymmetric memory dual-channel upgrade supported
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128-Mb, 256-Mb, 512-Mb technologies implemented as x8, x16 devices
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Up to 4 GB system memory
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Supports up to 16 simultaneously-open pages (four per row) in
dual-channel mode and up to 32 open pages in single-channel mode
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DDR (Double Data Rate type 1) Support
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Supports maximum of two DDR DIMMs per channel, single-sided
and/or double-sided
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Supports DDR266, DDR333, DDR400 DIMM modules
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Supports DDR channel operation at 266 MHz, 333 MHz and 400 MHz
with a Peak BW of 2.1 GB/s, 2.7 GB/s, and 3.2GB/s respectively per
channel
Communication Streaming Architecture (CSA) Interface
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Gigabit Ethernet (GbE) communication devices supported on the CSA
interface
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Supports 8-bit Hub Interface 1.5 electrical/transfer protocol
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266 MB/s point-to-point connection
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1.5 V operation
Hub Interface (HI)
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Supports Hub Interface 1.5 electrical/transfer protocol
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266 MB/s point-to-point connection to the ICH5
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66 MHz base clock
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1.5 V operation