IEI Technology IMBA-8654, Руководство пользователя

Страница: 179 / 242

IMBA-8654 Motherboard
Page 161
DRAM RAS# Precharge [4 Clocks]
Use the DRAM RAS# Precharge option to set the speed at which the RAM terminates the
access of one row and start accessing another. To be able to change this configuration
option the Configure DRAM Timing by SPD configuration option must be set to
“ Disabled .” The following configuration options are available
4 DRAM Clocks D
EFAULT
3 DRAM Clocks
2 DRAM Clocks
DRAM RAS# to CAS# Delay [4 Clocks]
Use the DRAM RAS# to CAS# Delay option to specify the number of clock cycles must
elapse between sending a RAS (row address strobe) signal and the CAS (column address
strobe) signal. A pause is required between the RAS signal and the CAS signal to ensure
the memory is correctly addressed. To be able to change this configuration option the
Configure DRAM Timing by SPD configuration option must be set to “ Disabled .”
Configuration options are listed below:
4 DRAM Clocks D
EFAULT
3 DRAM Clocks
2 DRAM Clocks
DRAM RAS# Precharge Delay [8 Clocks]
Use the DRAM RAS# Precharge Delay option to specify the length of the delay between
the activation and precharge commands for the RAS signal. That is how long after
activation can the access cycle be started again. This influences row activation time that is
considered when memory has hit the last column in a specific row, or when an entirely
different memory location is requested. To be able to change this configuration option the
Configure DRAM Timing by SPD configuration option must be set to “ Disabled .” The
following configuration options are available:
8 DRAM Clocks D
EFAULT
7 DRAM Clocks