IDT TSI384, Руководство пользователя

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10. Reset, Clocking, and Initialization 112
Tsi384 User Manual
May 5, 2014 Integrated Device Technology
www.idt.com
10.1.1 PCIe Link Reset
PCIe resets flow from upstream devices. The PCIe Interface is a slave to resets through a system-level
power-on reset controller connected to PCIE_PERSTn, or through inband messages from the root
complex. After release of reset the external EEPROM is loaded. During the loading process,
configuration requests will receive a “configuration request retry status” completion status.
10.1.1.1 Cold Reset – Level 0
A cold reset is applied after power up. This is a traditional power-on reset that is generally driven at the
system level by a power-on reset controller. After release of PCIE_PERSTn, all of Tsi384’s registers
are in their power-on reset state, including sticky bits. Clock (PCIE_REFCLK_n/p) and power must be
valid prior to the release of PCIE_PERSTn. The timing diagram for a cold reset is displayed in
Figure 24 , while its values are listed in Table 27 .
Figure 24: Reset Timing
10.1.1.2 Warm Reset – Level 0
A warm reset occurs without cycling power. This is achieved by bringing PCIE_PERSTn low for the
minimum specified time, T
perst
. After release of PCIE_PERSTn, all of Tsi384’s registers are in there
power-on reset state, including sticky bits.
Table 27: Reset Timing
Parameter Value Min./Max. Description
T
pvperl
10 ms Minimum Power valid to release of reset
T
perst-clk
10 ms Minimum Clock valid to releases of reset
T
perst
1 ms Minimum Minimum pulse for reset (warm reset)
T
fail
1 ms Maximum Time to assert reset after power is not valid
Tp vp erl
PCIE_PERSTn
Clo ck Valid
PWR Valid
Tper st-clk Tper st Tfail