IDT 89HPES48T12G2, Руководство пользователя

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Notes
PES48T12G2 User Manual 5 - 1 April 5, 2013
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Chapter 5
Reset and Initialization
Introduction
This chapter describes the PES48T12G2 reset and initialization.
When multiple resets are initiated concurrently, the precedence shown in Table 6.1 is used to determine
which one is acted upon.
– Reset types and causes are described in detail in the following sections.
• A switch fundamental reset affects the entire device
• A port reset affects only that one port
– When a high priority and low priority reset are initiated concurrently and the condition causing the
high priority reset ends prior to that causing the low priority reset, then the device/port immediately
transitions to the reset associated with low priority reset condition.
• If the high priority and low priority resets share the same reset type, then the device/port remains
in the corresponding reset when the high priority reset condition ends.
• If the high priority and low priority reset have different reset types, then the device/port transi-
tions to the low priority reset type when the high priority reset condition ends.
Registers and fields designated as Switch Sticky (SWSticky) or Sticky (Sticky) take on their initial value
as a result of the Switch Fundamental Reset. Other resets have no effect on registers and fields with these
designations.
All fields designated as Read Write when Unlocked (RWL) are implicitly SWSticky. Their value is
preserved across all resets except a switch fundamental reset.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 5.2 is sampled during a switch funda-
mental reset. Since the boot configuration vector is only sampled during a switch fundamental reset, the
value of signals that make up the boot configuration vector is ignored and their state outside of a switch
fundamental reset sequence has no effect on the operation of the device.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require more complex initialization. This initialization may be performed by an external
SMBus device via the slave SMBus interface or may be performed automatically via the serial EEPROM.
See Chapter 12, SMBus Interfaces, for a description of the slave SMBus interface and serial EEPROM
operation.
Priority Reset Type Reset cause
1 (Highest) Switch fundamental reset Global reset pin (PERSTN) assertion
2 Hot reset Reception of TS1 ordered sets on upstream port indicat-
ing a hot reset
3 Hot reset Data link layer of the upstream port transitioning to
DL_Down state
4 Upstream secondary bus reset Setting of the SRESET bit in the switch’s upstream port
PCI-to-PCI bridge BCTL register
5 (Lowest) Downstream secondary bus
reset
Setting of the SRESET bit in the corresponding port’s
PCI-to-PCI bridge BCTL register
Table 5.1 PES48T12G2 Reset Precedence