IDT 89HPES48T12G2, Руководство пользователя, Страница: 267 / 276

Notes
PES48T12G2 User Manual 17 - 1 April 5, 2013
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Chapter 17
JTAG Boundary Scan
Introduction
The JTAG Boundary Scan interface provides a way to test the interconnections between integrated
circuit pins after they have been assembled onto a circuit board.
There are two pin types present in the switch: AC-coupled and DC-coupled (also called AC and DC
pins). IEEE 1149.1 compliant boundary scan allows testing of the DC pins. The DC pins are the “normal”
pins that do not require AC-coupling. The presence of AC-coupling capacitors on some of the device pins
prevents DC values from being driven between a driver and receiver. AC Boundary Scan methodology
described in IEEE 1149.6, is available to provide a time-varying signal to pass through the AC-coupling
when in AC test mode. The IDT device supports both of these standards.
Test Access Point
The system logic utilizes a 16-state, TAP controller, a six-bit instruction register, and five dedicated pins
to perform a variety of functions. The primary use of the JTAG TAP Controller state machine is to allow the
five external JTAG control pins to control and access the switch's many external signal pins. The JTAG TAP
Controller can also be used for identifying the device part number. The JTAG logic of the switch is depicted
in Figure 17.1.
Figure 17.1 Diagram of the JTAG Logic
Refer to the IEEE 1149.1 document for an operational description of the Boundary Scan and TAP
controller.
Signal Definitions
JTAG operations such as reset, state-transition control, and clock sampling are handled through the
signals listed in Table 17.1. A functional overview of the TAP Controller and Boundary Scan registers is
provided in the sections following the table.
Bypass Register
Instruction Register Decoder
6-Bit Instruction Register
Tap Controller
m
u
x
m
u
x
Device ID Register
Boundary Scan Register
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TRST_N
JTAG_TDO