IDT 89HPES48T12G2, Руководство пользователя

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IDT Switch Core
PES48T12G2 User Manual 3 - 3 April 5, 2013
Notes
Crossbar Interconnect
The crossbar is an 12x12 matrix of pathways, capable of concurrently transferring data between a
maximum of 12 port pairs. The crossbar interconnects the port ingress buffers to the egress buffers. It
provides two data-interfaces per port, one for the port’s ingress buffers and one for the port’s egress
buffers.
Figure 3.1 shows the interface between the crossbar and a port’s ingress and egress buffers. The
crossbar is able to support 12 simultaneous data transfers. This architecture is well suited for system inter-
connect applications, as it allows simultaneous full-duplex communication between up to 12 peer devices.
Note there are no ports 10 and 11 in this device.
Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers
Datapaths
As mentioned earlier, the Switch Core interfaces with 12 ports. The interface between each port and the
switch core can be logically divided into ingress data interface, egress data interface.
The ingress data interface transfers data received by the port from the PCIe link into the switch-core.
The egress data interface transfers data from the switch-core to the port. All data paths through the ingress
data interface, crossbar interconnect and egress data interface are 160-bits wide instead of the required
128-bits (i.e., a x8 Gen2 port requires a throughput of 128-bits per clock cycle). On the ingress data inter-
face, the Switch Core receives data from the port at a rate determined by the operational mode of the port
(merged or bifurcated) and the width and speed of the port’s link. Packets received from the port are stored
in the appropriate IFB queue. After being queued in an IFB
1
and undergoing ordering and arbitration, all
data transferred through the crossbar interconnect is transferred in a continuous TLP manner (i.e., the data
path is never multiplexed).
This choice of datapath width implies that the crossbar has 20% higher throughput than the throughput
required to service all ports. This “over-speed” ensures that inter-port messages (i.e., internal messages
exchanged by ports for switch management) do not affect the throughput of the PCIe links.
On the egress interface, data in the EFB is read by the port’s data link layer (i.e., DL) when it is chosen
to be transmitted on the link. If the port is in merged mode, the DL allocates all clock cycles to read data
from the EFB. However, depending on the negotiated link width not all clock cycles may be used to transfer
data. If the port is in bifurcated mode, the DL reads data from the appropriate EFB (i.e., each port has a
dedicated EFB). Again, depending on the negotiated link width, not all clock cycles may be used to transfer
data.
Packet Ordering
The PCI Express specification 2.0 contains packet ordering rules to ensure the producer/consumer
model is honored across a PCIe hierarchy and to prevent deadlocks. The Switch Core performs packet
ordering on a per-port basis, at the output of the ingress and egress buffers of each port (refer to Figure
3.1).
Port
Mode
Replay Buffer Storage
Limit
x4
Bifurcated
32 TLPs
x8
Merged
64 TLPs
Table 3.3 Replay Buffer Storage Limit
1.
Please refer to section Cut-Through Routing on page 3-5 for further information on conditions for cut-through
transfers to occur.