IBM ThinkPad R30, Руководство оператора

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Operator Guide
A-14
2. Connection of high order address lines between CPU cards and System Planar ASICs
3. Connection of high order address lines between System Planar ASICs and memory
chips.
This test consists of two sub-tests. Words manipulated / used are not restored at the end of
the test. This test is applied to all the memory cards which are present. In case of errors,
suitable error messages are displayed on the console. The following is a description of the
sub-tests.
Work Area Test This test calculates the memory address available on each board.
Then the first memory card is accessed and read-write-compare
operation is done for a memory location. If the comparison is OK,
then the test proceeds to check the next board. Otherwise a fatal
error message is displayed on the console.
Main Memory Cards Accessibility Test
This test checks whether the high order memory address lines are
open, stuck to level 0, or shorted to any other data line. This is done
in two phases:
First, in Write phase, different patterns will be written on the four
memory cards. This is verified to check the accessibility of the
boards.
In the Read phase, the values are read and the interference
between the boards is checked (if the value written for the first
board, appears when the second board is accessed).
If there are any errors in the preceding operations, they are displayed with suitable error
messages on the console.