I-Bus IBC 2600, Руководство пользователя

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Chapter 1 - Specifications
1-8 IBC 2600 User’s Guide
NOTE: DIMM modules must not exceed 1.2” in height.
All memory components and DIMMs used with the SBC must be PC-100
compliant, which means that they comply with Intel’s PC SDRAM specifi-
cations. These include the PC SDRAM Specification (memory compo-
nent specific), the PC Unbuffered DIMM Specification, the PC Registered
DIMM Specification and the PC Serial Presence Detect Specification.
MEMORY HOLE
The SBC supports a 1MB memory hole option at 512KB-640KB or
15MB-16MB.
ERROR CHECKING AND CORRECTION
The memory interface supports ECC modes via BIOS setting for multi-
ple-bit error detection and detection of all errors confined to a single
nibble.
PCI LOCAL BUS INTERFACE
The SBC is fully compliant with the PCI Local Bus 2.1 Specification. It
has optimized the PCI interface to allow the CPU to sustain the highest
possible bandwidth (greater than 100 MB/sec sustained) and low latency
of the PCI Bus. It supports PCI-to-PCI bridge technology, a pipelined
snoop ahead feature and improved PCI to DRAM write-back policy. The
PCI Local Bus interfaces to the CompactPCI Bus of the backplane and to
the on-board PCI Ultra2 SCSI controller and dual PCI 10/100Base-T
Ethernet controllers. The CompactPCI Bus interface to the backplane is
compliant with the PCI Industrial Computer Manufacturers Group
(PICMG) Specification.
Connectors J3, J4 and J5 of the CompactPCI Bus are utilized by the
SBC for connection to the rear I/O transition. The SBC and Rear I/O
Transition Module are designed so that the signals on J3, J4 and J5 must
be routed only through those connectors between the SBC and Rear I/O
Transition Module. No other connection of those signals should be made
on the backplane. Specifically, this SBC must not be used in conjunction
with a backplane that has signals on J3, J4 or J5 bussed to the SBC slot,
i.e., some H. 110 backplanes.