I-Bus IBC 2600, Руководство пользователя

Страница: 17 / 140

Chapter 1 - Specifications
1-7 IBC 2600 User’s Guide
For Celeron processors, a 128K unified, non-blocking second
level (L2) cache improves performance by reducing the average
memory access time and providing fast access to recently used
instructions and data.
DRAM MEMORY
The DRAM interface consists of two dual in-line memory module (DIMM)
sockets and supports auto detection of memory up to 512MB of Synchro-
nous DRAM (SDRAM). Minimum memory size is 8MB. The System BIOS
automatically detects memory type, size and speed.
The SBC uses industry standard 64-bit or 72-bit wide gold finger DIMM
DRAM in two 168-pin DIMM sockets.
NOTE: Memory can be installed in one or both DIMM sockets. If only one
DIMM module is used, it must be populated in Bank 0 (BK0) if it is a 8MB
or 16MB DIMM module; single DIMMs of all other sizes must be popu-
lated in Bank 1 (BK1). If two modules are used, they must be the same
DIMM type, but may be different sizes (see table below). EDO DIMMs
are not supported. All DIMMs must have gold contacts.
The SBC supports DIMM memory modules which are PC-100 compliant
and have the following features:
S
168-pin DIMMs with gold-plated contacts
S
100MHz SDRAM
S
Non-ECC (64-bit) or ECC (72-bit) memory
S
3.3 volt
S
Single or double-sided DIMMs in the sizes listed below
S
Buffered or Registered configuration
DIMM
Size DIMM Type Non-ECC ECC
8MB Unbuffered 1M x 64 1M x 72
16MB Unbuffered 2M x 64 2M x 72
32MB Unbuffered 4M x 64 4M x 72
64MB Unbuffered 8M x 64 8M x 72
128MB Unbuffered 16M x 64 16M x 72
256MB Registered 32M x 64 32M x 72