HP Vectra VL800, Техническое справочное руководство

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3 System Board
The Input/Output Controller Hub 2 (82801BA)
Timer/Counter Block
The timer/counter block contains three counters that are equivalent in
function to those found in one 82C54 programmable interval counter/timer.
These three counters are combined to provide the system timer function,
and speaker tone. The 14.318 MHz oscillator input provides the clock source
for these three counters.
Advanced Programmable
Interrupt Controller
Incorporated in the ICH2, the APIC can be used in either single-processor or
multi-processor systems, while the standard interrupt controller supports
only single-processor systems.
Real Time Clock
The RTC is 146818A-compatible, with 256 bytes of CMOS. The RTC
performs two key functions: keeping track of the time of day and storing
system data.
The RTC operates on a 32.768 kHz crystal and a separate 3V lithium battery
that provides up to 6 years of protection for an unplugged system. It also
supports two lockable memory ranges. By setting bits in the configuration
space, two 8-byte ranges can be locked to read and write accesses. This
prevents unauthorized reading of passwords or other security information.
Another feature is a date alarm allowing for a schedule wake-up event up to
30 days in advance.
Enhanced Power
Management
The ICH2’s power management functions include enhanced clock control,
local and global monitoring support for 14 individual devices, and various
low-power (suspend) states. A hardware-based thermal management circuit
permits software-independent entry points for low-power states.
The ICH2 includes full support for the Advanced Configuration and Power
Interface (ACPI) specifications.
Devices on the SMBus
The SMBus is a subset of the I
2
C bus. It is a two-wired serial bus which runs
at a maximum speed of 100 kHz. It is used to monitor some of the hardware
functions of the system board (such as voltage levels, temperature, fan
speed, memory presence and type), both at system boot and during normal
run-time. It is controlled by the SMBus controller located in the ICH2.