HP Vectra VL800, Техническое справочное руководство

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3 System Board
Memory Controller Hub (82850)
RDRAM Interface
The MCH provides optional System bus error checking for data, address,
request and response signals. Only 400 MHz Direct Rambus (PC800)
devices are supported in any of 128 or 256 Mbit technology. 128 Mbit
RDRAM uses page sizes of 1 kbytes, while 256 Mbit devices target 1 kbyte or
2 kbyte pages.
A maximum number of 32 Rambus devices (128 Mbit technology implies 1
GB maximum in 32 MB increments, 256 Mbit technology implies 2 GB
maximum in 64 MB increments) are supported on the Direct Rambus
channel without external logic.
The MCH also provides optional data integrity features including ECC in the
memory array. During RDRAM writes, ECC is generated on a QWord (64 bit)
basis. During RDRAM reads, the MCH supports multiple-bit error detection
and single-bit error correction when the ECC mode is enabled.
MCH will scrub single bit errors by writing the corrected value back into
RDRAM for all reads when hardware scrubbing is enabled. This, however
does not include reads launched in order to satisfy an AGP aperture
transaction.
ECC can only be enabled when all RDRAM devices are populated in a system
that supports the extra two data bits used to store the ECC code.
Dual Rambus Bus
The Dual Rambus bus is comprised of 16 x 2 bits of data information, and
1 x 2 bits of Error Correcting Code (ECC). The bus is connected to the
RIMM memory slots and to the MCH chip supporting two Dual Rambus
channels (A and B).
Both channels run 400 MHz supporting up to 32 rambus devices per
channel. The maximum available data bandwidth is 3.2 GB/s at 400 MHz.
The configuration of both primary rambus channels must be symmetrical –
the memory configuration on channel A must be identical to the memory
configuration on channel B. This means the memory must be installed in
identical pairs.