HP Vectra VL800, Техническое справочное руководство

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53
3 System Board
Memory Controller Hub (82850)
The following table shows the features that are available in the MCH Host
Bridge/Controller.
Feature Feature
•
Processor/System Bus:
❒
Supports Pentium 4 processor at: 100 MHz System Bus
frequency (400 MHz Data Bus).
❒
Provides an 8-deep In-Order Queue supporting up to eight
outstanding transaction requests on the System bus.
❒
Desktop optimized AGTL+ bus driver technology with
integrated AGTL + termination resistors.
❒
Support for 32-bit System bus address.
•
Accelerated Graphics Port (AGP) Interface:
❒
Single 1.5V AGP connector.
❒
AGP Rev 2.0 compliant, including AGP 4x data transfers and
2x/4x Fast Write protocol.
❒
AGP 1.5V connector support with 1.5 V signalling only.
❒
AGP PIPE
#
or SBA initiated accesses to RDRAM is not
snooped
❒
AGP FRAME initiated accesses to RDRAM are snooped
(snooper identifies that data is coherent in cache memory).
❒
Hierarchical PCI configuration mechanism.
❒
Delayed transaction support for AGP-to-RDRAM reads that
cannot be serviced immediately.
•
Direct Rambus Memory Controller.
❒
Dual Direct Rambus Channels operating in lock-step (both
channels must be populated with a memory module).
Supporting 300 MHz or 400 MHz.
❒
RDRAM 128 Mb, 256 Mb devices.
❒
Minimum upgrade increment of 32 MB using 128 Mbit
RDRAM technology.
❒
Up to 64 Direct Rambus devices.
Dual channel maximum memory array size is:
— 1 GB using 128 Mbit RDRAM technology.
— 2 GB using 256 Mbit RDRAM technology.
❒
Up to 8 simultaneous open pages:
— 1 KByte page size support for 128 Mbit and 256 Mbit
RDRAM devices.
— 2 KByte page size support for 256 Mbit RDRAM devices.
•
Power management:
❒
RDRAM space re-mapping to A0000h - BFFFFh (128 KB).
❒
Extended RDRAM space above 256 MB, additional 128 K,
256 K, 512 K, 1 MB TSEG from Top of Memory, cacheable
(cacheability controlled by processor).
❒
Suspend to RAM.
❒
ACPI Rev. 1.0 compliant power management.
❒
APM Rev. 1.2 compliant power management.
❒
Power-managed states are supported.
•
Hub Link 8-bit Interface to ICH2:
❒
High-speed interconnect between the MCH and ICH2
(266 MB/sec).
•
Arbitration:
❒
Distributed Arbitration Model for Optimum Concurrency
Support.
❒
Concurrent operations of System, hub interface, AGP and
memory buses supported via a dedicated arbitration and
data buffering logic.
•
615 OLGA MCH package.
•
Input/Output Device Support:
❒
Input/Output Controller Hub (ICH2).