HP 9000 V-Class, Руководство оператора

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Chapter 1 5
Overview
The node
Control and status registers (CSRs)
System hardware is manipulated by control and status registers, CSRs,
located in the processors and controllers.
CSRs provide control, status, or both to the processors and other
hardware in the node. Each CSR is memory mapped and is available to
all processors in the system. Many of the registers are described in detail
throughout this book by functional groups, such as system configuration,
messaging and data copy, error recovery, and so on.
Description of functional blocks
Each block in Figure 1 is described in the following sections.
Processor agent controller
The EPAC can connect to zero, one, or two PA-8200 processors. It can
also connect to zero or one EPIC (the I/O controller). With no processors,
the EPAC serves as an I/O-only interface. The EPAC has the following
buses:
Runway bus (0, 1)—Two each, 64-bit, bidirectional buses for processor 0
and processor 1, respectively. These buses have a raw bandwidth of 960
Mbytes/sec.
Hyperplane crossbar port bus (0, 1)—Four 32-bit, unidirectional buses
connected to two Hyperplane crossbar ERACs, two in each direction.
These buses have a total raw bandwidth of 1.9 Gbytes/sec.
I/O port—Two 16-bit or 32-bit, unidirectional interfaces to an I/O device,
one for reading data and one for writing data. The width of the bus
depends on the width of the I/O device connected. Each bus has a
bandwidth of 120 Mbytes/sec or 240 Mbytes/sec, depending on the width
of the interface.
Core Logic Bus interface—Bidirectional bus that supports boot and
support services.
The EPAC sends and receives transactions from the ERACs using four
unidirectional data paths. There are four ERACs in the Hyperplane
crossbar. Each processor agent, however, communicates with only two of
the four ERACs.