HP 8560A, Руководство по обслуживанию

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4. Step the Video BW down to Hz. At each step, the amplitude of the LO feedthrough
should decrease.
5. Refer to Table 7-7 and check for correct latch settings for the selected video bandwidth
setting.
6. If latch output is not correct, trigger an oscilloscope on pin 9)
and monitor pin 1 and other latch inputs while changing the video bandwidth.
7. If the inputs are incorrect, troubleshoot the analog bus. Correct inputs with bad outputs
indicate a faulty
8. Check that the outputs of and are correct for
their inputs. The outputs should be high with noninverting inputs higher than the V
threshold voltage. If a voltage drop is noticed across these components, suspect
or
Since no dc current flows through any of the series resistances or FETS
(drain to source), no voltage drops should occur.
Table 7-7. Latch Outputs
Video BW
300
Hz
3
30kHz
100
300
3 MHz
Pin2
H
L
L
L
H
L
L
L
L
Pin 5
L
L
H
L
L
L
H
L
L
Pin 7
L
L
L
L
H
H
H
H
L
Pin 10 Pin 12
L L
L L
L
L
L H
L L
L L
L L
L H
H L
Pin 15
L
H
L
L
L
H
L
L
L
Video Filter Buffer Amplifier
See function block W of A3 Interface Assembly Schematic Diagram (sheet 5 of 6).
The video filter buffer amplifier provides outputs for video trigger, positive and negative
peak detectors, and the analog zero-span (sweeps
ms). The zero-span video
output is terminated in 500 ohms on the A2 Controller assembly. The amplifier is a
high-input-impedance buffer amplifier with a gain of one when properly terminated.
Current source provides twice the current of Q316. Resistor R145 and current source
shift the dc level. Resistor R260 terminates the peak detector inputs in 500 ohms. The
unterminated gain is 1.1. Diode CR114 prevents during positive overdrive conditions
while CR113 protects Q318 during overdrive. Diode CR117 is a 12.7 V zener that limits the
peak detector’s output to
V. Typically, limiting occurs at V.
7-16 Section