HMS FlexRay CCM, Руководство по программированию

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Copyright IXXAT Automation GmbH
UCI Programming Manual FlexRay, V1.13
Annex
58
UCI_FLXHDRINFO_
VALID-
COMMUNICATION-
EVENT
Active FIFO Buffer
AFBMBSSVR
bit 7 (VCE)
FIFO Slot Status
MBSS
bit 7 (VFA)

CH A
bit 15 (VFB)

CH B
UCI_FLXHDRINFO_
SYNTAXERROR Active FIFO Buffer
AFBMBSSVR
bit 3 (SERR)
FIFO Slot Status
MBSS
bit 3 (SEA)

CH A
bit 11 (SEB)

CH B
UCI_FLXHDRINFO_
CONTENTERROR Active FIFO Buffer
AFBMBSSVR
bit 2 (CERR) FIFO Slot Status
MBSS
bit 2 (CEA)

CH A
bit 10 (CEB)

CH B
UCI_FLXHDRINFO_
BOUNDARY-
VIOLATION Active FIFO Buffer
AFBMBSSVR
bit 1 (BVIOL) FIFO Slot Status
MBSS
bit 1 (BVA)

CH A
bit 9 (BVB)

CH B
UCI_FLXHDRINFO_
TXCONFLICT
Active Transmit Buffer
ATBMBSSVR
bit 0 (TXCON)
Transmit Buffer Slot
Status
MBSS
bit 0 (TCA)

CH A
bit 8 (TCB)

CH B
UCI_FLXHDRINFO_
FRAMETYPE from UCI INI File
Determined from
Number of static slots
(static / dynamic)
NSSR
bit 0-10 (NSSR)
from UCI INI File
Determined from num-
ber of static slots
(static / dynamic)
PCR2
bit 0-10 (number_of_
static_slots)
UCI_FLXHDRINFO_
SELFRECEPTION UCI internal message
type
(TX Acknowledge)
UCI internal message
type
(TX Acknowledge 2)
UCI_FLXHDRINFO_
BOTHCHANNELS from UCI INI File
static and dynamic
(TX Msg) from UCI INI File
static only
(TX Msg)
UCI_FLXHDRINFO_
ASYNCMODE UCI internal *1) UCI internal
Active Transmit Buffer
AFBMBSSVR
bit 13 (ASYNC)
*2)
Transmit Buffer Slot
Status 2
MBSS2
bit 8 (ASYNC)