System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode
timings on the main memory interface:
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tCL = CAS Latency
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tRCD = Activate Command to READ or WRITE Command delay
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tRP = PRECHARGE Command Period
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CWL = CAS Write Latency
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Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new
command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and
memory configuration.
System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel. Depending upon how the
SO-DIMM Modules are populated in each memory channel, a number of different configurations can exist.
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the
system, as determined through the SPD registers on the memory modules. The system memory controller supports
only one SO-DIMM connector per channel. For dual-channel modes both channels must have an SO DIMM
connector populated. For single-channel mode, only a single-channel can have an SO-DIMM connector populated.
