4.9 Power Management Interface Signals –Table 1
Name
Type
Description
PLTRST#
O
Platform Reset:
The Ibex Peak asserts PLTRST# to reset
devices on the platform (e.g., SIO, FWH, LAN, Processor,
etc.). The Ibex Peak asserts PLTRST# during power-up and
when S/W initiates a hard reset sequence through the Reset
Control register (I/O Register CF9h). The Ibex Peak drives
PLTRST# inactive a minimum of 1 ms after both PWROK and
VGATE are driven high. The Ibex Peak drives PLTRST#
active a minimum of 1 ms when initiated through the Reset
Control register (I/O Register CF9h).
NOTE:
PLTRST# is in the VccSus3_3 well.
THRMTRIP#
I
Thermal Trip:
When low, this signal indicates that a thermal
trip from the processor occurred, and the Ibex Peak will
immediately transition to a S5 state. The Ibex Peak will not
wait for the processor stop grant cycle since the processor has
overheated.
SLP_S3#
O
S3 Sleep Control:
SLP_S3# is for power plane control. This
signal shuts off power to all non-critical systems when in S3
(Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off)
states.
SLP_S4#
O
S4 Sleep Control:
SLP_S4# is for power plane control. This
signal shuts power to all non-critical systems when in the S4
(Suspend to Disk) or S5 (Soft Off) state.
NOTE:
This pin must be used to control the DRAM power in
order to use the Ibex Peak’s DRAM power-cycling feature.
