Watchdog Timer Control Register (Offset 0x8)
Bit
Name
Access
Default
Description
7:02
—
R
0x00
Reserved
1:0
LOCK
R/W
0
Watchdog timer lock
0: Unlocked
1: Locked
0:0
EN
R/W
0
Watchdog timer enable
0: Disabled
1: Enabled
The Reload register provides a means to service the Watchdog timer while it is enabled.
Watchdog Timer Reload Register (Offset 0xA)
Bit
Name
Access
Default
Description
7:01
—
R
0x00
Reserved
0:0
RELOAD
R/W
0
Writing a 1 reloads the
Watchdog timer with the value
in the Interrupt Count register.
Always reads back 0.
The Status register indicates whether the Watchdog interrupt and reset timers have
expired. The reset indication is a sticky bit that is not cleared on a system reset, although
it is cleared on powerup.
Watchdog Timer Status Register (Offset 0xC)
Bit
Name
Access
Default
Description
7:02
—
R
0b000000
Reserved
1:0
EXP_RST
R/C
0
Reset timer expired. When
1, indicates that the
Watchdog reset timer has
expired. Cleared by writing
a 1 to the bit. Sticky bit that
retains its value through a
system reset.
0:0u
EXP_SERIRQ
R/C
0
SERIRQ timer expired.
When 1, indicates that the
Watchdog timer has
expired an issued an
interrupt. Cleared by writing
a 1 to the bit.
Watchdog Timer Interrupt Enable Register (Offset 0xE)
Bit
Name
Access
Default
Description
7:01
—
R
0b0000000
Reserved
0:0
EN_SERIRQ
RW
0
Enable SERIRQ
1 = Enable SERIRQ
0 = Disable SERIRQ
72
GFK-2896
Mini COM Express Type 10 Module mCOM10-L1500
For public disclosure
Содержание Mini COM Express 10
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