PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
40
Freescale Semiconductor
MPC8313E RDB Board Configuration
4–7
SPMF[0–3]
System PLL
multiplication factor
0000
Reserved
0001
Reserved
0010 (Default)
2:1
0011
3:1
0100
4:1
0101
5:1
4–7
SPMF[0–3]
System PLL
multiplication factor
0110
6:1
0111-1111
Reserved
8
—
Reserved
Must be cleared.
9–15
COREPLL
[0–6]
Value
coreclk: csb_clk
VCO divider
nn 0000 0
PLL bypassed
PLL bypassed
00 0001 0
1:1
2
01 0001 0
1:1
4
10 0001 0
1:1
8
00 0001 1
1.5:1
2
01 0001 1
1.5:1
4
10 0001 1
1.5:1
8
00 0010 0 (Default)
2:1
2
9–15
COREPLL
[0–6]
01 0010 0
2:1
4
10 0010 0
2:1
8
00 0010 1
2.5:1
2
01 0010 1
2.5:1
4
10 0010 1
2.5:1
8
00 0011 0
3:1
2
01 0011 0
3:1
4
10 0011 0
3:1
8
16–31
—
Reserved.
Must be cleared.
Table 19. RCWL Bit Descriptions (continued)
Bits
Name
Meaning
Description
