PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
12
Freescale Semiconductor
Board-Level Functions
voltage regulator. VREF, which is half the interface voltage, or 0.9 V, is provided by a voltage divider of
1.8 V for voltage tracking and low cost. The MPC8313E provides a pair of clock pins, which are connected
and shared by the two DDR2 devices.
Figure 7
shows the DDR2 SDRAM controller connection.
Figure 7. DDR2 SDRAM Connection
2.5
Local Bus Controller
The MPC8313E local bus controller has a 26-bit LAD[0–15] and LA[16–25] address that consists of
16-bit data multiplex bus and control signals. The local bus speed is up to 133 MHz. To interface with the
standard memory device, an address latch must provide the address signals. The LALE is used as the
latching signal. To reduce loading of the high speed local bus interface, a data buffer for all low-speed
devices is attached to the memory controller. The followings modules are connected to the local bus:
•
8 Mbyte NOR flash memory
•
32 Mbyte NAND flash memory
•
LED/status buffers
2.5.1
NOR Flash Memory
Through the general-purpose chip-select machine (GPCM), the MPC8313E RDB provides 8 Mbyte of
flash memory using a chip-select signal. The flash memory is used with the 16-bit port size.
Figure 8
DDR2 Device (512 Mbit, 16-Bit)
MPC8313E
DDR2
Controller
DDR2 Device (512 Mbit, 16-Bit)
MCS0
MCK, MCK, MCKE
MRAS, MCAS, MWE
MDM[0:3], MDQS[0:3]
A[0:14], BA[0:2]
MDQ[0:31]
ODT
VREF
1.8 V Reg
VREF
