PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
26
Freescale Semiconductor
Connectors, Jumpers, Switches, and LEDs
3.10
DIP Switch S3
DIP switch S3 selects the reset configuration source (RST_CFG_SRC) for the MPC8313E.
Figure 27
shows the factory default configuration of S3.
Figure 27. DIP Switch S3
Check the MPC8313E reference manual for the meaning of the CFG_RST_SRC combination. By default,
the DIP switch is set to all ON, meaning CFG_RST_SRC[0..3] = 0000. In this case, the hardware reset
configuration is loaded from local bus NOR flash memory.
3.11
DIP Switch S4
DIP switch S4 on the RDB is shown in
Figure 28
, with the factory default configuration.
Figure 28. DIP Switch S4
RSVD is reserved. When software options are implemented, their values can be read from a buffer on the
board. CFG_BOOT_ECC_DIS switch is OFF by default to disable booting with ECC by driving HIGH to
1
2
3
4
ON
CFG_RST
_
SRC0
0
1
CFG_RST_
SRC1
C
F
G
_
RST_SRC2
CF
G
_
RST_SRC3
1
2
3
4
ON
0
1
RSVD
REV1
BOO
T
1
(
N
AND)
CFG_BOO
T
_ECC_DI
S
