PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
Freescale Semiconductor
47
Frequently Asked Questions (FAQs)
user to achieve a successful re-installation of the BSP on the MPC8313E RDB. This ISO image contains
the following documents as well:
•
MPC8313ERDBUG.pdf
. This user's guide document in PDF format.
•
MPC8313E-RDB_schematic.pdf
. The platform schematic in PDF format.
•
SEC2SWUG.pdf
. User's guide for the driver software of the security engine. This document details the
driver software interface to boost the throughput performance of security applications such as
IPSec.
•
LtibFaq.pdf
. Frequently asked questions for LTIB, which is a useful document describing how to
use LTIB to build the ISO image.
For more information on the MPC8313E RDB, visit the Freescale website listed on the back cover of this
document. To run demonstrations or to acquire details of Freescale third-party applications for this
MPC8313E RDB, contact your local Freescale sales office.
8
Frequently Asked Questions (FAQs)
Here are some commonly asked questions and their respective answers.
8.1
What are the differences among RDB revisions?
There are five revisions of the RDB, which are REVA, REVA1, REVA2, REVA3, REVA4, REVB and
REVC.
Table 24
lists and describes these revisions.
Table 24. MPC8313E-RBD Revisions
Revision
Description
REVA
There are two major issues on the REVA board:
• On-chip PHY USB signals (DP, DM) are swapped. To use the USB, use a USB cable that swaps the signals
(the cable is attached in the REVA package).
• NAND flash memory cannot be used as a boot device.
REVA1
Fixes both major issues on the REVA board. The boot-from-NAND on the REVA1 RDB has been verified.
However, on the current BSP preloaded on REVA1 RDB, NAND flash memory is empty, so it is also not
bootable. Booting from NAND flash memory will be supported in a future release of the BSP.
Software for REVA and REVA1 differs only in the OR1[BCTLD] register setting for NAND flash memory. That
is, REVA OR1[BCTLD] is 1; while REVA1 OR1[BCTLD] is 0.
REVA2
A minor update from REVA1 for mass production. It updates the silkscreen and adds a 12-V fan connector
(J25) and resistor loading for ATX power.
Software can be shared without modification between REVA1 and REVA2.
REVA3
Fixes the PMC register issue mentioned in
Section 8.5, “Power management control (PMC) registers cannot
be accessed?
”
Because of a processor erratum, a 166 MHz CSB frequency should be used. For this reason, some REVA3
and all later boards have 33 MHz instead of 66 MHz as the clock input (check your board U15 oscillator
marking). The CORE/CSB/DDR frequency setting is 333/166/333 MHz. However, there are two drawbacks:
• PCI bus can run at up to only 33 MHz
• PCI/mini-PCI card can run at 66 MHz (has its M66EN pulled up) and should be used. Even the PCI bus on
the RDB runs at only 33 MHz. Otherwise, the PCI frequency is further divided and it becomes 16.6 MHz.
