PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
50
Freescale Semiconductor
Revision History
3
3/2008
• Added GTX_CLK125 sourced from external 125 MHz oscillator.
• Added an optional IEEE 1588 connector (P10).
• Added three more resistor options (R311–R313) to route three IEEE 1588 signals that are
only available in eTSEC1 to the IEEE 1588 connector.
• Changed S4 to support LB_POR_CFG_BOOT_ECC_DIS.
• Changed SD chip select signal from SPISEL(GPIO31) to GPIO13.
4
8/2008
• Added a Marvell 88E1111 PHY. Phy address assigned to 0x3. Use same IRQ3# as L2
Switch.
• Added resistor option for RGMII signals route to either to L2 Switch or Marvell 88E1111
PHY.
• Added SGMII support for eTSEC1 if using the added Marvell 88E1111 PHY. (SGMII for
eTSEC2 already supported.)
• Added PLL CY23EP05SXC-1 U86 to PHY gerneated 125 MHz clock.
• Changed default TSEC1_GTX_CLK125 clock source to PLL CY23EP05SX-1 instead of
external 125 MHZ oscillator.
• Changed U36 1A linear regulator MIC39100-2.5WS to 3A MIC37302WR for higher 2.5V
power consumption by additional PHY.
• Changed default DAC to 16-bit SPI controlled MAX5 (U47).
Table 25. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
