PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
8
Freescale Semiconductor
Board-Level Functions
2.1
Reset and Reset Configurations
The MPC8313E RDB reset module generates a single reset to the MPC8313E and other peripherals on the
board. The reset unit provides power-on reset, hard reset, and soft reset signals in compliance with the
MPC8313E hardware specification.
Figure 4
shows the reset circuitry. Note the following:
•
Hard reset is generated either by the COP/JTAG port or the MPC8313E.
•
Power-on reset is generated by the Maxim MAX811 device. When MR is deasserted and 3.3 V is
ready, the MAX811 internal timeout guarantees a minimum reset active time of 150 ms before
PORESET is deasserted. This circuitry guarantees a 150 ms PORESET pulse width after 3.3 V
reaches the right voltage level, which meets the specification of the PORESET input of
MPC8313E.
•
COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller. The
RESET line is available at the COP/JTAG port connector. The COP/JTAG controller can directly
generate the hard-reset signal by asserting this line low.
•
Push button reset interfaces using the MR signal with debounce capability to produce a manual
master reset of the RDB.
•
Soft reset is generated by the COP/JTAG port. Assertion of SRESET causes the MPC8313E to
abort all current internal and external transactions and set most registers to their default values.
Figure 4. Reset Circuitry of the MPC8313E
MAX811
3.3 V
MR
Push Button
GND
HRESET from COP
SRESET from COP
TRST from COP
SRESET to MPC8313E
TRST to MPC8313E
PORESET to MPC8313E
NOR FLASH
L2 Switch
MPC8313E
Reset config logic
Marvell PHY
