9.4.1 IR Codes
Table 9-3. JTAG Instructions
Instruction
Code[3:0]
Instruction Summary
IDCODE
0000
Selects device identification register for shift
SAMPLE/PRELOAD
0010
Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
SAMPLE
0011
Selects boundary scan register for shifting and sampling
without disturbing functional operation
EXTEST
0100
Selects boundary scan register while applying preloaded
values to output pins and asserting functional reset
HIGHZ
1001
Selects bypass register while three-stating all output pins and
asserting functional reset
CLAMP
1100
Selects bypass register while applying preloaded values to
output pins and asserting functional reset
EZPORT
1101
Enables the EZPORT function for the SoC and asserts
functional reset.
ARM_IDCODE
1110
ARM JTAG-DP Instruction
BYPASS
1111
Selects bypass register for data operations
Factory debug reserved
0101, 0110, 0111
Intended for factory debug only
ARM JTAG-DP Reserved
1000, 1010, 1011, 1110 These instructions will go the ARM JTAG-DP controller.
Please look at ARM JTAG-DP documentation for more
information on these instructions.
Reserved
All other opcodes
Decoded to select bypass register
1. The manufacturer reserves the right to change the decoding of reserved instruction codes in the future
9.5 JTAG status and control registers
Through the ARM Debug Access Port (DAP), the debugger has access to the status and
control elements, implemented as registers on the DAP bus as shown in the following
figure. These registers provide additional control and status for low power mode recovery
and typical run-control scenarios. The status register bits also provide a means for the
debugger to get updated status of the core without having to initiate a bus transaction
across the crossbar switch, thus remaining less intrusive during a debug session.
It is important to note that these DAP control and status registers are not memory mapped
within the system memory map and are only accessible via the Debug Access Port (DAP)
using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with
the available registers shown in the table below.
Table 9-4. MDM-AP Register Summary
Address
Register
Description
Table continues on the next page...
JTAG status and control registers
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
198
Freescale Semiconductor, Inc.
Содержание MK22FN256VDC12
Страница 2: ...K22F Sub Family Reference Manual Rev 3 7 2014 2 Freescale Semiconductor Inc...
Страница 136: ...Human machine interfaces K22F Sub Family Reference Manual Rev 3 7 2014 136 Freescale Semiconductor Inc...
Страница 164: ...Module clocks K22F Sub Family Reference Manual Rev 3 7 2014 164 Freescale Semiconductor Inc...
Страница 246: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 246 Freescale Semiconductor Inc...
Страница 328: ...Kinetis Flashloader Status Error Codes K22F Sub Family Reference Manual Rev 3 7 2014 328 Freescale Semiconductor Inc...
Страница 360: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 360 Freescale Semiconductor Inc...
Страница 388: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 388 Freescale Semiconductor Inc...
Страница 402: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 402 Freescale Semiconductor Inc...
Страница 500: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 500 Freescale Semiconductor Inc...
Страница 670: ...Flash memory map for EzPort access K22F Sub Family Reference Manual Rev 3 7 2014 670 Freescale Semiconductor Inc...
Страница 680: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 680 Freescale Semiconductor Inc...
Страница 744: ...Application information K22F Sub Family Reference Manual Rev 3 7 2014 744 Freescale Semiconductor Inc...
Страница 784: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 784 Freescale Semiconductor Inc...
Страница 794: ...Initialization Application Information K22F Sub Family Reference Manual Rev 3 7 2014 794 Freescale Semiconductor Inc...
Страница 960: ...Example configuration for chained timers K22F Sub Family Reference Manual Rev 3 7 2014 960 Freescale Semiconductor Inc...
Страница 1036: ...Device mode IRC48 operation K22F Sub Family Reference Manual Rev 3 7 2014 1036 Freescale Semiconductor Inc...
Страница 1040: ...USB Voltage Regulator Module Signal Descriptions K22F Sub Family Reference Manual Rev 3 7 2014 1040 Freescale Semiconductor Inc...
Страница 1094: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 1094 Freescale Semiconductor Inc...
Страница 1128: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 1128 Freescale Semiconductor Inc...
Страница 1216: ...Application information K22F Sub Family Reference Manual Rev 3 7 2014 1216 Freescale Semiconductor Inc...
Страница 1298: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 1298 Freescale Semiconductor Inc...
Страница 1312: ...K22F Sub Family Reference Manual Rev 3 7 2014 1312 Freescale Semiconductor Inc...