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22.4.4.3 eDMA performance example

Consider a system with the following characteristics:

• Internal SRAM can be accessed with one wait-state when viewed from the system

bus data phase

• All internal peripheral bus reads require two wait-states, and internal peripheral bus

writes three wait-states viewed from the system bus data phase

• System operates at 150 MHz

For an SRAM to internal peripheral bus transfer,

PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec

For an internal peripheral bus to SRAM transfer,

PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec

Assuming an even distribution of the two transfer types, the average peak request rate
would be:

PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec

The minimum number of cycles to perform a single read/write, zero wait states on the
system bus, from a cold start where no channel is executing and eDMA is idle are:

• 11 cycles for a software, that is, a TCDn_CSR[START] bit, request

• 12 cycles for a hardware, that is, an eDMA peripheral request signal, request

Two cycles account for the arbitration pipeline and one extra cycle on the hardware
request resulting from the internal registering of the eDMA peripheral request signals.
For the peak request rate calculations above, the arbitration and request registering is
absorbed in or overlaps the previous executing channel.

Note

When channel linking or scatter/gather is enabled, a two cycle
delay is imposed on the next channel selection and startup. This
allows the link channel or the scatter/gather channel to be
eligible and considered in the arbitration pool for next channel
selection.

Chapter 22 Enhanced Direct Memory Access (eDMA)

K22F Sub-Family Reference Manual , Rev. 3, 7/2014

Freescale Semiconductor, Inc.

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Содержание MK22FN256VDC12

Страница 1: ...K22F Sub Family Reference Manual Supports MK22FN256VDC12 MK22FN256VLL12 MK22FN256VMP12 MK22FN256VLH12 Document Number K22P121M120SF8RM Rev 3 7 2014...

Страница 2: ...K22F Sub Family Reference Manual Rev 3 7 2014 2 Freescale Semiconductor Inc...

Страница 3: ...Module Functional Categories 49 2 2 1 ARM Cortex M4 Core Modules 50 2 2 2 System Modules 51 2 2 3 Memories and Memory Interfaces 52 2 2 4 Clocks 52 2 2 5 Security and Integrity modules 52 2 2 6 Analog...

Страница 4: ...SMC Configuration 68 3 3 3 PMC Configuration 68 3 3 4 Low Leakage Wake up Unit LLWU Configuration 69 3 3 5 MCM Configuration 71 3 3 6 Crossbar Light Switch Configuration 71 3 3 7 Peripheral Bridge Con...

Страница 5: ...Controller Configuration 87 3 5 3 SRAM Configuration 87 3 5 4 System Register File Configuration 89 3 5 5 VBAT Register File Configuration 90 3 5 6 EzPort Configuration 90 3 6 Security 91 3 6 1 CRC C...

Страница 6: ...Universal Serial Bus USB FS Subsystem 118 3 9 2 SPI configuration 123 3 9 3 I2C Configuration 127 3 9 4 UART Configuration 128 3 9 5 LPUART configuration 130 3 9 6 I2S configuration 131 3 10 Human ma...

Страница 7: ...8 5 4 1 Device clock summary 149 5 5 Internal clocking requirements 152 5 5 1 Clock divider values after reset 153 5 5 2 VLPR mode clocking 153 5 6 Clock Gating 154 5 7 Module clocks 154 5 7 1 PMC 1 k...

Страница 8: ...t sequence 175 Chapter 7 Power Management 7 1 Introduction 177 7 2 Clocking modes 177 7 2 1 Partial Stop 177 7 2 2 DMA Wakeup 178 7 2 3 Compute Operation 179 7 2 4 Peripheral Doze 180 7 2 5 Clock Gati...

Страница 9: ...uence 196 9 2 2 JTAG to cJTAG change sequence 196 9 3 Debug Port Pin Descriptions 197 9 4 System TAP connection 197 9 4 1 IR Codes 197 9 5 JTAG status and control registers 198 9 5 1 MDM AP Control Re...

Страница 10: ...4 1 Core Modules 218 10 4 2 System Modules 219 10 4 3 Clock Modules 219 10 4 4 Memories and Memory Interfaces 220 10 4 5 Analog 220 10 4 6 Timer Modules 221 10 4 7 Communication Interfaces 223 10 4 8...

Страница 11: ...register definition 248 12 2 1 System Options Register 1 SIM_SOPT1 249 12 2 2 SOPT1 Configuration Register SIM_SOPT1CFG 251 12 2 3 System Options Register 2 SIM_SOPT2 252 12 2 4 System Options Registe...

Страница 12: ...oader 13 1 Chip Specific Information 279 13 2 Introduction 279 13 3 Functional Description 281 13 3 1 Memory Maps 281 13 3 2 Kinetis Flashloader 281 13 3 3 Start up Process 282 13 3 4 Clock Configurat...

Страница 13: ...337 Chapter 15 System Mode Controller SMC 15 1 Introduction 339 15 2 Modes of operation 339 15 3 Memory map and register descriptions 341 15 3 1 Power Mode Protection register SMC_PMPROT 342 15 3 2 P...

Страница 14: ...LLWU 17 1 Introduction 369 17 1 1 Features 369 17 1 2 Modes of operation 370 17 1 3 Block diagram 371 17 2 LLWU signal descriptions 372 17 3 Memory map register definition 372 17 3 1 LLWU Pin Enable...

Страница 15: ...MCM_PLACR 391 18 2 4 Interrupt Status and Control Register MCM_ISCR 392 18 2 5 Compute Operation Control Register MCM_CPO 395 18 3 Functional description 396 18 3 1 Interrupts 396 Chapter 19 Crossbar...

Страница 16: ...with periodic triggering capability 409 21 4 2 DMA channels with no triggering capability 411 21 4 3 Always enabled DMA sources 411 21 5 Initialization application information 413 21 5 1 Reset 413 21...

Страница 17: ...2 3 14 Error Register DMA_ERR 453 22 3 15 Hardware Request Status Register DMA_HRS 456 22 3 16 Enable Asynchronous Request in Stop Register DMA_EARS 459 22 3 17 Channel n Priority Register DMA_DCHPRIn...

Страница 18: ...l Linking Disabled DMA_TCDn_BITER_ELINKNO 475 22 4 Functional description 476 22 4 1 eDMA basic data flow 476 22 4 2 Fault reporting and handling 479 22 4 3 Channel preemption 481 22 4 4 Performance 4...

Страница 19: ...23 4 5 EWM Refresh Mechanism 509 23 4 6 EWM Interrupt 510 23 4 7 Counter clock prescaler 510 Chapter 24 Watchdog Timer WDOG 24 1 Introduction 511 24 2 Features 511 24 3 Functional overview 513 24 3 1...

Страница 20: ...High WDOG_TMROUTH 526 24 7 10 Watchdog Timer Output Register Low WDOG_TMROUTL 526 24 7 11 Watchdog Reset Count register WDOG_RSTCNT 527 24 7 12 Watchdog Prescaler register WDOG_PRESC 527 24 8 Watchdo...

Страница 21: ...ram 548 25 4 2 Low power bit usage 553 25 4 3 MCG Internal Reference Clocks 553 25 4 4 External Reference Clock 554 25 4 5 MCG Fixed Frequency Clock 554 25 4 6 MCG PLL clock 555 25 4 7 MCG Auto TRIM A...

Страница 22: ...lator OSC32K 27 1 Introduction 581 27 1 1 Features and Modes 581 27 1 2 Block Diagram 581 27 2 RTC Signal Descriptions 582 27 2 1 EXTAL32 Oscillator Input 582 27 2 2 XTAL32 Oscillator Output 582 27 3...

Страница 23: ...8 4 10 Cache Data Storage upper word FMC_DATAW1SnU 604 28 4 11 Cache Data Storage lower word FMC_DATAW1SnL 605 28 4 12 Cache Data Storage upper word FMC_DATAW2SnU 605 28 4 13 Cache Data Storage lower...

Страница 24: ...d Writes 633 29 4 7 Read While Write RWW 634 29 4 8 Flash Program and Erase 634 29 4 9 Flash Command Operations 634 29 4 10 Margin Read Commands 638 29 4 11 Flash Command Description 639 29 4 12 Secur...

Страница 25: ...egister CRC_CTRL 674 31 3 Functional description 675 31 3 1 CRC initialization reinitialization 675 31 3 2 CRC calculations 676 31 3 3 Transpose feature 677 31 3 4 CRC result complement 679 Chapter 32...

Страница 26: ...ory map and register definitions 695 33 3 1 ADC Status and Control Registers 1 ADCx_SC1n 697 33 3 2 ADC Configuration Register 1 ADCx_CFG1 700 33 3 3 ADC Configuration Register 2 ADCx_CFG2 702 33 3 4...

Страница 27: ...Minus Side General Calibration Value Register ADCx_CLM3 715 33 3 22 ADC Minus Side General Calibration Value Register ADCx_CLM2 716 33 3 23 ADC Minus Side General Calibration Value Register ADCx_CLM1...

Страница 28: ...definitions 750 34 2 1 CMP Control Register 0 CMPx_CR0 750 34 2 2 CMP Control Register 1 CMPx_CR1 751 34 2 3 CMP Filter Period Register CMPx_FPR 753 34 2 4 CMP Status and Control Register CMPx_SCR 75...

Страница 29: ...a High Register DACx_DATnH 776 35 4 3 DAC Status Register DACx_SR 777 35 4 4 DAC Control Register DACx_C0 778 35 4 5 DAC Control Register 1 DACx_C1 779 35 4 6 DAC Control Register 2 DACx_C2 780 35 5 F...

Страница 30: ...7 1 4 DAC External Trigger Input Connections 797 37 1 5 Block diagram 797 37 1 6 Modes of operation 799 37 2 PDB signal descriptions 799 37 3 Memory map and register definition 799 37 3 1 Status and C...

Страница 31: ...resolution 814 Chapter 38 FlexTimer Module FTM 38 1 Introduction 815 38 1 1 FlexTimer philosophy 815 38 1 2 Features 816 38 1 3 Modes of operation 817 38 1 4 Block diagram 818 38 2 FTM signal descript...

Страница 32: ...FLTCTRL 855 38 3 21 Quadrature Decoder Control And Status FTMx_QDCTRL 858 38 3 22 Configuration FTMx_CONF 860 38 3 23 FTM Fault Input Polarity FTMx_FLTPOL 861 38 3 24 Synchronization Configuration FTM...

Страница 33: ...21 Initialization trigger 924 38 4 22 Capture Test mode 926 38 4 23 DMA 927 38 4 24 Dual Edge Capture mode 928 38 4 25 Quadrature Decoder mode 935 38 4 26 BDM mode 940 38 4 27 Intermediate load 941 3...

Страница 34: ...on information 957 39 6 Example configuration for chained timers 958 Chapter 40 Low Power Timer LPTMR 40 1 Introduction 961 40 1 1 Features 961 40 1 2 Modes of operation 961 40 2 LPTMR signal descript...

Страница 35: ...er RTC_TPR 974 41 2 3 RTC Time Alarm Register RTC_TAR 974 41 2 4 RTC Time Compensation Register RTC_TCR 975 41 2 5 RTC Control Register RTC_CR 976 41 2 6 RTC Status Register RTC_SR 978 41 2 7 RTC Lock...

Страница 36: ...er definitions 999 42 4 1 Peripheral ID register USBx_PERID 1001 42 4 2 Peripheral ID Complement register USBx_IDCOMP 1002 42 4 3 Peripheral Revision register USBx_REV 1002 42 4 4 Peripheral Additiona...

Страница 37: ...register USBx_OBSERVE 1021 42 4 26 USB OTG Control register USBx_CONTROL 1021 42 4 27 USB Transceiver Control register 0 USBx_USBTRC0 1022 42 4 28 Frame Adjust Register USBx_USBFRMADJUST 1023 42 4 29...

Страница 38: ...heral Chip Selects 1 3 1047 44 2 3 PCS4 Peripheral Chip Select 4 1047 44 2 4 PCS5 PCSS Peripheral Chip Select 5 Peripheral Chip Select Strobe 1047 44 2 5 SCK Serial Clock 1047 44 2 6 SIN Serial Input...

Страница 39: ...78 44 4 5 Continuous Serial Communications Clock 1083 44 4 6 Slave Mode Operation Constraints 1084 44 4 7 Interrupts DMA requests 1085 44 4 8 Power saving features 1087 44 5 Initialization application...

Страница 40: ...45 3 10 I2C Address Register 2 I2Cx_A2 1109 45 3 11 I2C SCL Low Timeout Register High I2Cx_SLTH 1109 45 3 12 I2C SCL Low Timeout Register Low I2Cx_SLTL 1110 45 4 Functional description 1110 45 4 1 I2...

Страница 41: ...3 11 UART Control Register 4 UARTx_C4 1151 46 3 12 UART Control Register 5 UARTx_C5 1152 46 3 13 UART Extended Data Register UARTx_ED 1153 46 3 14 UART Modem Register UARTx_MODEM 1154 46 3 15 UART In...

Страница 42: ...B UARTx_WP7816B_T0 1171 46 3 36 UART 7816 Wait Parameter Register B UARTx_WP7816B_T1 1171 46 3 37 UART 7816 Wait and Guard Parameter Register UARTx_WGP7816_T1 1172 46 3 38 UART 7816 Wait Parameter Reg...

Страница 43: ...47 1 4 Block diagram 1219 47 2 Register definition 1220 47 2 1 LPUART Baud Rate Register LPUARTx_BAUD 1221 47 2 2 LPUART Status Register LPUARTx_STAT 1223 47 2 3 LPUART Control Register LPUARTx_CTRL 1...

Страница 44: ...1264 48 3 7 SAI Transmit Data Register I2Sx_TDRn 1264 48 3 8 SAI Transmit FIFO Register I2Sx_TFRn 1265 48 3 9 SAI Transmit Mask Register I2Sx_TMR 1265 48 3 10 SAI Receive Control Register I2Sx_RCSR 12...

Страница 45: ...49 2 Memory map and register definition 1291 49 2 1 Port Data Output Register GPIOx_PDOR 1293 49 2 2 Port Set Output Register GPIOx_PSOR 1294 49 2 3 Port Clear Output Register GPIOx_PCOR 1294 49 2 4 P...

Страница 46: ...n register 1303 50 3 2 Bypass register 1303 50 3 3 Device identification register 1303 50 3 4 Boundary scan register 1304 50 4 Functional description 1305 50 4 1 JTAGC reset configuration 1305 50 4 2...

Страница 47: ...y different numbering systems This suffix Identifies a b Binary number For example the binary equivalent of the number 5 is written 101b In some cases binary numbers are shown with the prefix 0b d Dec...

Страница 48: ...by a colon represent either A subset of a register s named field For example REVNO 6 4 refers to bits 6 4 that are part of the COREREV field that occupies bits 6 0 of the REVNO register A continuous...

Страница 49: ...ntegration module Power management and mode controllers Multiple power modes available based on high speed run run wait stop and power down modes Low leakage wakeup unit Miscellaneous control module C...

Страница 50: ...the ARMv7 Architecture and Thumb 2 ISA and is upward compatible with the Cortex M3 Cortex M1 and Cortex M0 architectures Cortex M4 improvements include an ARMv7 Thumb 2 DSP ported from the ARMv7 A R p...

Страница 51: ...VD trip points Low leakage wakeup unit LLWU The LLWU module allows the device to wake from low leakage power modes LLS and VLLS through various internal peripheral and external pin sources Miscellaneo...

Страница 52: ...wing clock modules are available on this device Table 2 5 Clock modules Module Description Multi clock generator MCG The MCG provides several clock sources for the MCU that include Phase locked loop P...

Страница 53: ...successive approximation ADC Analog comparators Compares two analog input voltages across the full range of the supply voltage 6 bit digital to analog converters DAC 64 tap resistor ladder network wh...

Страница 54: ...insertion is available for each complementary pair Generation of hardware triggers Software control of PWM outputs Up to 4 fault inputs for global fault control Configurable channel polarity Programm...

Страница 55: ...to communicate with a variety of serial devices such as standard codecs digital signal processors DSPs microprocessors peripherals and audio codecs that implement the inter IC sound bus I2S and the I...

Страница 56: ...1 This part number is subject to removal Orderable part numbers K22F Sub Family Reference Manual Rev 3 7 2014 56 Freescale Semiconductor Inc...

Страница 57: ...ific module to module interactions not necessarily discussed in the individual module chapters and links for more information 3 2 Core modules 3 2 1 ARM Cortex M4 Core Configuration This section summa...

Страница 58: ...upts Nested Vectored Interrupt Controller NVIC NVIC Private Peripheral Bus PPB module Miscellaneous Control Module MCM MCM Private Peripheral Bus PPB module Single precision floating point unit FPU FP...

Страница 59: ...e only available source of reference timing 3 2 1 3 Debug facilities This device has extensive debug capabilities including run control and tracing capabilities The standard ARM debug port that suppor...

Страница 60: ...s 16 priority levels for interrupts Therefore in the NVIC each source in the IPR registers contains 4 bits For example IPR0 is shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Страница 61: ...e Debug Monitor 0x0000_0034 13 0x0000_0038 14 ARM core Pendable request for system service PendableSrvReq 0x0000_003C 15 ARM core System tick timer SysTick Non Core Vectors 0x0000_0040 16 0 0 0 DMA DM...

Страница 62: ...LS recovery 0x0000_0098 38 22 0 5 WDOG or EWM Both watchdog modules share this interrupt 0x0000_009C 39 23 0 5 RNG Randon Number Generator 0x0000_00A0 40 24 0 6 I2C0 0x0000_00A4 41 25 0 6 I2C1 0x0000_...

Страница 63: ...0110 68 52 1 13 PDB 0x0000_0114 69 53 1 13 USB OTG 0x0000_0118 70 54 1 13 0x0000_011C 71 55 1 13 0x0000_0120 72 56 1 14 DAC0 0x0000_0124 73 57 1 14 MCG 0x0000_0128 74 58 1 14 Low Power Timer 0x0000_01...

Страница 64: ...NVIC s interrupt source number 2 Indicates the NVIC s ISER ICER ISPR ICPR and IABR register number used for this IRQ The equation to calculate this value is IRQ div 32 3 Indicates the NVIC s IPR regis...

Страница 65: ...Power management Power management Nested Vectored Interrupt Controller NVIC NVIC Wake up requests AWIC wake up sources 3 2 3 1 Wake up sources The device uses the following internal and external inpu...

Страница 66: ...an external bit clock or external master clock NMI Non maskable interrupt 3 2 4 FPU Configuration This section summarizes how the module has been configured in the chip For a comprehensive descriptio...

Страница 67: ...g Port control Signal multiplexing 3 3 System modules 3 3 1 SIM Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itsel...

Страница 68: ...d chapter Power Management Controller PMC Register access Peripheral bridge System Mode Controller SMC Resets Figure 3 7 System Mode Controller configuration Table 3 11 Reference links to related info...

Страница 69: ...d in the chip For a comprehensive description of the module itself see the module s dedicated chapter Low Leakage Wake up Unit LLWU Power Management Controller PMC Peripheral bridge 0 Register access...

Страница 70: ...P10 PTC6 LLWU_P10 pin LLWU_P11 PTC11 LLWU_P11 pin LLWU_P12 PTD0 LLWU_P12 pin LLWU_P13 PTD2 LLWU_P13 pin LLWU_P14 PTD4 LLWU_P14 pin LLWU_P15 PTD6 LLWU_P15 pin LLWU_M0IF LPTMR2 LLWU_M1IF CMP02 LLWU_M2IF...

Страница 71: ...le Reference Full description Miscellaneous control module MCM MCM System memory map System memory map Clocking Clock distribution Power management Power management Transfers Private Peripheral Bus PP...

Страница 72: ...Full description Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Crossbar switch master ARM Cortex M4 core ARM Cortex M4 core Crossbar switch master DMA...

Страница 73: ...3 6 2 Crossbar Light Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows Slave module Slave port number Flash memory controller 0 SRAM controllers 1 2 Periphe...

Страница 74: ...rossbar switch 3 3 7 1 Number of peripheral bridges This device contains one peripheral bridge 3 3 7 2 Memory maps The peripheral bridges are used to access the registers of most of the modules on thi...

Страница 75: ...DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels Because of the mux there is not a hard correlation between any of the DMA request sources and a spec...

Страница 76: ...l 0 21 FTM0 Channel 1 22 FTM0 Channel 2 23 FTM0 Channel 3 24 FTM0 Channel 4 25 FTM0 Channel 5 26 FTM0 Channel 6 27 FTM0 Channel 7 28 FTM1 Channel 0 29 FTM1 Channel 1 30 FTM2 Channel 0 31 FTM2 Channel...

Страница 77: ...abled 62 DMA MUX Always enabled 63 DMA MUX Always enabled 1 Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel 3 3 8 2 DMA transfers via PIT trigger...

Страница 78: ...map System memory map Register access Peripheral bridge AIPS Lite 0 AIPS Lite 0 Clocking Clock distribution Power management Power management Transfers Crossbar switch Crossbar switch 3 3 10 External...

Страница 79: ...ent Power management Signal multiplexing Port Control Module Signal multiplexing 3 3 10 1 EWM clocks This table shows the EWM clocks and the corresponding chip clocks Table 3 22 EWM clock connections...

Страница 80: ...ter WDOG Mode Controller Peripheral bridge 0 Register access Figure 3 15 Watchdog configuration Table 3 24 Reference links to related information Topic Related module Reference Full description Watchd...

Страница 81: ...chip low power modes Table 3 26 WDOG low power modes Module mode Chip mode Wait Wait VLPW Stop Stop VLPS Power Down LLS VLLSx 3 4 Clock modules 3 4 1 MCG Configuration This section summarizes how the...

Страница 82: ...referred to as the external reference clock and selection is determined by MCG_C7 OSCSEL bitfield The following table shows the chip specific clock assignments for this bitfield Table 3 28 MCG Oscill...

Страница 83: ...memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3 4 2 1 OSC modes of operation...

Страница 84: ...he chip For a comprehensive description of the module itself see the module s dedicated chapter Register access Flash memory Transfers Flash memory controller Peripheral bus controller 0 Figure 3 19 F...

Страница 85: ...FF MK22FN256VLH12 256 0x0000_0000 0x0003_FFFF 1 This part number is subject to removal 3 5 1 3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as show...

Страница 86: ...en the EzPort is enabled EZP_CS asserted during reset Otherwise flash memory operates in NVM normal mode 3 5 1 7 Erase All Flash Contents An Erase All Flash Blocks operation can be launched by softwar...

Страница 87: ...ontroller Flash memory controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch Register access Peripher...

Страница 88: ...n the memory map anchored at address 0x2000_0000 As such SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address SRAM_U is anchored to 0x2000_0000 and occupies the space af...

Страница 89: ...ripheral bridge 0 Register access Figure 3 23 System Register file configuration Table 3 34 Reference links to related information Topic Related module Reference Full description Register file Registe...

Страница 90: ...emory map System memory map Clocking Clock distribution Power management Power management 3 5 5 1 VBAT register file This device includes a 32 byte register file that is powered in all power modes and...

Страница 91: ...ort mode 3 5 6 2 Flash Option Register FOPT The FOPT EZPORT_DIS bit can be used to prevent entry into EzPort mode during reset If the FOPT EZPORT_DIS bit is cleared then the state of the chip select s...

Страница 92: ...on Table 3 37 Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3 6 2 RNG Configurati...

Страница 93: ...m memory map System memory map Clocking Clock distribution Power management Power management 3 7 Analog 3 7 1 16 bit SAR ADC Configuration This section summarizes how the module has been configured in...

Страница 94: ...nnels The number of ADC channels present on the device is determined by the pinout of the specific device package For details regarding the number of ADC channel available on a particular package refe...

Страница 95: ...d Reserved 001007 AD4b Reserved ADC0_SE4b 001017 AD5b Reserved ADC0_SE5b 001107 AD6b Reserved ADC0_SE6b 001117 AD7b Reserved ADC0_SE7b 01000 AD8 Reserved ADC0_SE88 01001 AD9 Reserved ADC0_SE99 01010 A...

Страница 96: ...e voltage and not the VREF module 1 2 V reference voltage Prior to reading from this ADC channel ensure that you enable the bandgap buffer by setting the PMC_REGSC BGBE bit Refer to the device data sh...

Страница 97: ...odule Disabled 1 Interleaved with ADC0_DP3 and ADC0_DM3 2 Interleaved with ADC0_DP3 3 Interleaved with ADC0_DP0 and ADC0_DM0 4 Interleaved with ADC0_DP0 5 ADCx_CFG2 MUXSEL bit selects between ADCx_SEn...

Страница 98: ...the following configuration ADC0 AD8 AD9 ADC1 AD8 AD9 ADC0_SE8 ADC1_SE8 ADC0_SE9 ADC1_SE9 Figure 3 30 ADC hardware interleaved channels integration There are other pins on this device that have a simi...

Страница 99: ...triggering the ADC is the PDB The PDB itself can be triggered by other peripherals For example RTC Alarm Seconds signal is connected to the PDB The PDB input trigger can receive the RTC alarm seconds...

Страница 100: ...for this bitfield NOTE The ALTCLK option is only usable when OSCERCLK is in the MHz range A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequ...

Страница 101: ...ated chapter Signal multiplexing Module signals Register access CMP Peripheral bridge 0 Other peripherals Figure 3 31 CMP configuration Table 3 45 Reference links to related information Topic Related...

Страница 102: ...st first enable the CMP and DAC prior to performing a CMP operation and capturing the output In this device control for this two staged sequencing is provided from the LPTMR The LPTMR provides a singl...

Страница 103: ...configuration Table 3 47 Reference links to related information Topic Related module Reference Full description 12 bit DAC 12 bit DAC System memory map System memory map Clocking Clock distribution Po...

Страница 104: ...chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Module signals Register access VREF Peripheral bus controller 0 Other peripherals Tran...

Страница 105: ...guration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Module signa...

Страница 106: ...0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 initialization trigger and channel triggers as programmed in the FTM external trigger register EXTTRIG 1001 FTM1 init...

Страница 107: ...acknowledgement input ADC1SC1B_COCO PDB channel 0 trigger pre trigger 1 acknowledgement input ADC0SC1A_COCO PDB channel 1 trigger pre trigger 0 acknowledgement input ADC0SC1B_COCO PDB channel 1 trigg...

Страница 108: ...are connected to each CMP block and used for sample window 3 8 1 7 Pulse Out Enable Register Implementation The following table shows the comparison of pulse out enable register at the module and chip...

Страница 109: ...se modules are configured Table 3 54 FTM Instantiations FTM instance Number of channels Features usage FTM0 8 3 phase motor 2 general purpose or stepper motor FTM1 21 Quadrature decoder or general pur...

Страница 110: ...in or CMP1 output FTM0 FAULT2 FTM0_FLT2 pin FTM0 FAULT3 FTM0_FLT3 pin FTM1 FAULT0 FTM1_FLT0 pin or CMP0 output FTM1 FAULT1 CMP1 output FTM2 FAULT0 FTM2_FLT0 pin or CMP0 output FTM2 FAULT1 CMP1 output...

Страница 111: ...e USB Interrupt Enable register INTEN SOFTOKEN to avoid USB enumeration conflicts 3 8 2 8 FTM Hall sensor support For 3 phase motor control sensor ed applications the use of Hall sensors generally 3 s...

Страница 112: ...SRC that allow the user to select normal PWM Output Compare mode on the corresponding FTM timer channel or modulate with FTM1_CH1 The diagram below shows the implementation for FTM0 See SIM Block Guid...

Страница 113: ...he PDB and ADC modules See PDB Instantiation and ADC triggers 3 8 2 11 FTM Global Time Base This chip provides the optional FTM global time base feature see Global time base GTB FTM0 provides the only...

Страница 114: ...ode 3 8 3 PIT Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Register acce...

Страница 115: ...ter 3 8 4 Low power timer configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter S...

Страница 116: ...filter clock number Chip clock 00 0 MCGIRCLK internal reference clock not available in VLPS LLS VLLS modes 01 1 LPO 1 kHz clock not available in VLLS0 mode 10 2 ERCLK32K secondary external reference...

Страница 117: ...odule Reference Full description RTC RTC System memory map System memory map Clocking Clock Distribution Power management Power management 3 8 5 1 RTC_CLKOUT signal When the RTC is enabled and the por...

Страница 118: ...s See VBUS detect IRC48 with clock recovery block to eliminate the 48MHz crystal This is available for USB device mode only USB controller FS LS transceiver USB voltage regulator D D VREGIN VOUT33 Fig...

Страница 119: ...ternal 5 V to 3 3 V USB regulator that powers the USB transceiver or the MCU depending on the application NOTE In the following examples VREGIN is used instead of VREG_IN0 Similarly VOUT33 is used ins...

Страница 120: ...connected to VDD The USB regulator must be enabled by default to power the MCU When connected to a USB host the input source of this regulator is switched to the USB bus supply from the Li ion battery...

Страница 121: ...mode 3 9 1 4 VBUS detect The USB FS controller does not include a dedicated VBUS detect pin However a GPIO pin with interrupt capability can be used to detect the presence of VBUS in device mode If a...

Страница 122: ...l description USB controller USB controller System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexi...

Страница 123: ...it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating 3 9 2 SPI configuration This section summarizes how the module has been configured in the chip For a comprehensive descr...

Страница 124: ...sters define different transfer attribute configurations The SPI module supports up to eight CTAR registers This device supports two CTARs on all instances of the SPI In master mode the CTAR registers...

Страница 125: ...e SPI In VLPR and VLPW modes the max SPI_CLK frequency is 2MHz In stop and VLPS modes the clocks to the SPI module are disabled The module is not functional but it is powered so that it retains state...

Страница 126: ...s Table 3 65 SPI clock connections Module clock Chip clock System Clock Bus Clock 3 9 2 11 Writing SPI Transmit FIFO The SPI supports 8 bit or 16 bit writes to the PUSH TX FIFO allowing a single write...

Страница 127: ...Module signals 2 I C Figure 3 51 I2C configuration Table 3 66 Reference links to related information Topic Related module Reference Full description I2C I2C System memory map System memory map Clockin...

Страница 128: ...ignal Multiplexing 3 9 4 1 UART configuration information This chip contains three UART modules This section describes how each module is configured on this device 1 Standard features of all UARTs RS...

Страница 129: ...UART 2 Transmit data empty x x x Transmit complete x x x Idle line x x x Receive data full x x x LIN break detect x x x RxD pin active edge x x x Initial character detect x The error interrupt combin...

Страница 130: ...related information Topic Related module Reference Full description LPUART0 LPUART System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexin...

Страница 131: ...odule Reference Full description I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing 3 9 6 1...

Страница 132: ...equests 3 9 6 2 4 I2S SAI clock generation Each SAI peripheral can control the input clock selection pin direction and divide ratio of one audio master clock The MCLK Input Clock Select bit of the MCL...

Страница 133: ...alization of any of the I2S SAI registers 3 9 6 3 I2S SAI operation in low power modes 3 9 6 3 1 Stop and very low power modes In Stop mode the SAI transmitter and or receiver can continue operating p...

Страница 134: ...Entry into stop mode is prevented not acknowledged while waiting for the transmitter and receiver to be disabled at the end of the current frame 3 10 Human machine interfaces 3 10 1 GPIO configuration...

Страница 135: ...available on the devices covered by this document are detailed in Orderable part numbers Eight GPIO pins support a high drive capability PTB0 PTB1 PTD4 PTD5 PTD6 PTD7 PTC3 and PTC4 All other GPIO sup...

Страница 136: ...Human machine interfaces K22F Sub Family Reference Manual Rev 3 7 2014 136 Freescale Semiconductor Inc...

Страница 137: ...s There is an aliased region that maps a system address space to the Program flash section Flash region aliasing is specifically intended for references to read only data coefficients in the flash whi...

Страница 138: ...Reserved 0x4200_0000 0x42FF_FFFF Aliased to peripheral bridge AIPS Lite bitband Cortex M4 core only 0x4300_0000 0x43FD_FFFF Reserved 0x43FE_0000 0x43FF_FFFF Aliased to general purpose input output GP...

Страница 139: ...en to the alias region determines what value is written to the target bit Writing a value with bit 0 set writes a 1 to the target bit Writing a value with bit 0 clear writes a 0 to the target bit A 32...

Страница 140: ...The unsecure state of user non secure aligns to no access control states set and the mid level state where user secure aligns to using the access control of execute only Control for this protection sc...

Страница 141: ...tools An alternate IRC trim to the factory loaded trim can be stored at this location To override the factory trim user software must load new values into the MCG trim registers Non Volatile Byte Addr...

Страница 142: ...these situations the application software must perform a read after write sequence to guarantee the required serialization of the memory operations 1 Write the peripheral register 2 Read the written...

Страница 143: ...4001_3000 19 0x4001_4000 20 0x4001_5000 21 0x4001_6000 22 0x4001_7000 23 0x4001_8000 24 0x4001_9000 25 0x4001_A000 26 0x4001_B000 27 0x4001_C000 28 0x4001_D000 29 0x4001_E000 30 0x4001_F000 31 Flash m...

Страница 144: ...0x4003_C000 60 0x4003_D000 61 Real time clock RTC 0x4003_E000 62 VBAT register file 0x4003_F000 63 DAC0 0x4004_0000 64 Low power timer LPTMR 0x4004_1000 65 System register file 0x4004_2000 66 0x4004_...

Страница 145: ...4000 100 Multi purpose Clock Generator MCG 0x4006_5000 101 System oscillator OSC 0x4006_6000 102 I2C 0 0x4006_7000 103 I2C 1 0x4006_8000 104 0x4006_9000 105 0x4006_A000 106 UART 0 0x4006_B000 107 UART...

Страница 146: ...p System 32 bit Address Range Resource 0xE000_0000 0xE000_0FFF Instrumentation Trace Macrocell ITM 0xE000_1000 0xE000_1FFF Data Watchpoint and Trace DWT 0xE000_2000 0xE000_2FFF Flash Patch and Breakpo...

Страница 147: ...ssipation Various modules such as the USB OTG Controller have module specific clocks that can be generated from the IRC48MCLK or MCGPLLCLK or MCGFLLCLK clock In addition there are various other module...

Страница 148: ...Clock options for some peripherals see note MCGFLLCLK MCGPLLCLK Note See subsequent sections for details on where these clocks are used PMC logic PMC LPO OSCCLK CG CG CG CG CG Clock gate RTC_CLKOUT C...

Страница 149: ...bus and flash clock It is also an option for the debug trace clock MCGFLLCLK MCG output of the FLL MCGFLLCLK may clock some modules MCGPLLCLK MCG output of the PLL MCGFLLCLK or MCGPLLCLK may clock so...

Страница 150: ...MCGOUTCLK clock divider In all stop modes and Compute Operation Bus clock Up to 60 MHz Up to 50 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode and Compute Ope...

Страница 151: ...clocking is possible via SIM_SOPT1 OSC3 2KOUT to drive CLKOUT32K out in all low power modes CLKOUT32K 32 kHz 32 kHz 32 kHz ERCLK32K which is system OSC or LPO or RTC OSC depending on SIM_SOPT1 OSC3 2...

Страница 152: ...RUN 80 MHz or slower in RUN 2 The bus clock frequency must be programmed to 60 MHz or less in HSRUN 50 MHz or less in RUN and an integer divide of the core clock The core clock to bus clock ratio is l...

Страница 153: ...the user flexibility for a lower frequency low power boot option The flash erased state defaults to fast clocking mode since where the low power boot FTF_FOPT LPBOOT bit resides in flash is logic 1 in...

Страница 154: ...e corresponding bit in SCGCx register to enable the clock Before turning off the clock make sure to disable the module Any bus access to a peripheral that has its clock disabled generates an error ter...

Страница 155: ...k EZP_CLK Security CRC Bus clock RNGA Bus clock Analog ADC Bus clock OSCERCLK IRC48MCLK CMP Bus clock DAC Bus clock VREF Flash clock Timers PDB Bus clock FlexTimers Bus clock MCGFFCLK FTM_CLKINx PIT B...

Страница 156: ...mode IRC48MCLK is forced disabled when the MCU transitions into VLPS LLSx and VLLSx low power modes NOTE IRC48MCLK is not forced disabled in Stop modes and should be disabled by software prior to Stop...

Страница 157: ...the USB Host If the IRC48M clock is selected as the source of the PLL with MCG_C7 OSCSEL 10 then the clock frequency of the system clocks can shift as the USB device connects to the USB Host starting...

Страница 158: ...figured to run from the 1 kHz LPO clock source PORTx_DFCR CS PORTx digital input filter clock Bus clock LPO Figure 5 4 PORTx digital input filter clock generation 5 7 6 LPTMR clocking The prescaler an...

Страница 159: ...KOUT is disabled in LLSx and VLLSx modes CLKOUT32K controlled by SIM_SOPT1 OSC32KOUT can also be driven on the pins where the RTC_CLKOUT signal is an option overriding the existing pin mux configurati...

Страница 160: ...RTC_CLKOUT and CLKOUT32K generation 5 7 8 USB FS OTG Controller clocking The USB FS OTG controller is a bus master attached to the crossbar switch As such it uses the system clock NOTE For the USB FS...

Страница 161: ...ver function enabled 5 7 9 UART clocking UART0 and UART1 modules operate from the core system clock which provides higher performance level for these modules All other UART modules operate from the bu...

Страница 162: ...ripheral can control the input clock selection pin direction and divide ratio of one audio master clock The I2S SAI transmitter and receiver support asynchronous bit clocks BCLKs that can be generated...

Страница 163: ...I BCLK_OUT BCD BCLK I2Sx_MDR FRACT DIVIDE I2Sx_MCR MICS Clock Generation DIV I2Sx_TCR2 RCR2 SIM_SOPT2 PLLFLLSEL 01 00 MCGFLLCLK Direction Control Pad Interface Logic Fractional Clock Divider 11 IRC48M...

Страница 164: ...Module clocks K22F Sub Family Reference Manual Rev 3 7 2014 164 Freescale Semiconductor Inc...

Страница 165: ...nerator loss of lock LOL reset Stop mode acknowledge error SACKERR Software reset SW Lockup reset LOCKUP EzPort reset MDM DAP system reset Debug reset JTAG reset nTRST reset Each of the system reset s...

Страница 166: ...start processing from a known set of initial conditions System reset begins with the on chip regulator in full regulation and system clocking generation from an internal reference When the processor e...

Страница 167: ...ontinued filtering operation depending on the filtering mode selected When entering VLLS0 the RESET pin filter is disabled and bypassed The LPO filter has a fixed filter value of 3 Due to a synchroniz...

Страница 168: ...age power modes The LLWU module is functional only in low leakage power modes In LLS mode only the RESET pin via the LLWU can generate a system reset In VLLSx modes all enabled inputs to the LLWU can...

Страница 169: ...ledge the entry to stop mode if an error condition occurs The error can be caused by a failure of an external clock input to a module 6 2 2 8 Software reset SW The SYSRESETREQ bit in the NVIC applicat...

Страница 170: ...stem reset This is the primary method for resets via the JTAG SWD interface The system reset is held until this bit is cleared Set the core hold reset bit in the MDM AP control register to hold the co...

Страница 171: ...sources except a VLLS Wakeup that does not occur via the RESET_b pin It resets parts of the SMC LLWU and other modules that remain powered during VLLS mode The Chip Reset not VLLS reset also causes th...

Страница 172: ...EXTEST HIGHZ and CLAMP instructions are active The reset source from the JTAG module is released when any other IR code is selected A JTAG reset causes the RCM s SRS1 JTAG bit to set 6 2 5 2 nTRST res...

Страница 173: ...2 Boot options The device s functional mode is controlled by the state of the EzPort chip select EZP_CS pin during reset The device can be in single chip default or serial flash programming mode EzPo...

Страница 174: ...speed on POR VLLSx and any system reset 0 Slower initialization The Flash initialization will be slower with the benefit of reduced average current during this time The duration of the recovery will...

Страница 175: ...age as determined by the LVD The Mode Controller reset logic then controls a sequence to exit reset 1 A system reset is held on internal logic the RESET pin is driven out low and the MCG is enabled in...

Страница 176: ...NMI input and the FOPT NMI_DIS field in the Flash Memory module If the NMI input is high or the NMI function is disabled in the NMI_DIS field the CPU begins execution at the PC location If the NMI inp...

Страница 177: ...ode When configured for PSTOP2 only the core and system clocks are gated and the bus clock remains active The bus masters and bus slaves clocked by the system clock enter Stop mode but the bus slaves...

Страница 178: ...ernal power switches enabling the clock generators in the MCG enabling the system and bus clocks but not the core clock and negating the stop mode signal to the bus masters and bus slaves The only dif...

Страница 179: ...ynchronous DMA request 7 2 3 Compute Operation Compute Operation is an execution or compute only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port but place...

Страница 180: ...cates when entry has completed When exiting Compute Operation in Run mode the CPOACK status bit negates immediately When exiting Compute Operation in VLP Run mode the exit is delayed to allow the PMC...

Страница 181: ...the corresponding bit in the SCGCx register to enable the clock Before turning off the clock make sure to disable the module For more details refer to the clock distribution and SIM chapters 7 3 Powe...

Страница 182: ...is in a low power mode that supplies only enough power to run the chip at a reduced frequency Sleep Interrupt VLPS Very Low Power Stop via WFI Places chip in static state with LVD operation off Lowest...

Страница 183: ...U and RTC can be used NVIC is disabled LLWU is used to wake up All of SRAM_U and SRAM_L are powered off The 32 byte system register file and 32 byte VBAT register file remain powered for customer crit...

Страница 184: ...tware must re initialize the I O pins to their pre low power mode entry states before releasing the hold If the oscillator was configured to continue running during VLLSx modes it must be re configure...

Страница 185: ...ted low power state All low power entry sequences are initiated by the core executing an WFI instruction The ARM core s outputs SLEEPDEEP and SLEEPING trigger entry to the various low power modes Syst...

Страница 186: ...l register As part of this transition system clocking is re established and is equivalent to normal run VLPR mode clocking configuration 7 7 Flash Program Restrictions The flash memory on this device...

Страница 187: ...ion Async operation static OFF Watchdog FF FF FF FF static OFF EWM FF static in CPO static static FF in PSTOP2 static static OFF Clocks 1kHz LPO ON ON ON ON ON ON in VLLS1 2 3 OFF in VLLS0 System osci...

Страница 188: ...static wakeup on resume static wakeup on resume static wakeup on resume static wakeup on resume static OFF USB Voltage Regulator optional optional optional optional optional optional UART0 UART1 250...

Страница 189: ...ALTCLK clocks only in CPO FF ADACK ALTCLK and ALTCLK2 clocks only FF in PSTOP2 ADACK and ALTCLK clocks only static OFF CMP9 FF HS or LS compare in CPO FF HS or LS compare FF in PSTOP2 HS or LS compare...

Страница 190: ...ding EXTAL 7 System OSC and LPO clock sources are not available in VLLS0 Pulse counting is available in all modes 8 RTC_CLKOUT is not available CLKOUT32K can be configured as an alternate path of supp...

Страница 191: ...security byte of the flash configuration field NOTE The security features apply only to external accesses via debug and EzPort CPU accesses to the flash are not affected by the status of FSEC In the...

Страница 192: ...y is enabled The mass erase can be used to disable flash security but all of the flash contents are lost in the process A mass erase via the EzPort is allowed even when some memory locations are prote...

Страница 193: ...nd other available resources Four debug interfaces are supported IEEE 1149 1 JTAG IEEE 1149 7 JTAG cJTAG Serial Wire Debug SWD ARM Real Time Trace Interface 1 pin asynchronous mode only The basic Cort...

Страница 194: ...n Module Description SWJ DP cJTAG Modified Debug Port with support for SWD JTAG cJTAG AHB AP AHB Master Interface from JTAG to debug module and SOC system memory maps MDM AP Provides centralized contr...

Страница 195: ...space Alternatively the six instruction comparators can individually configure the comparators to return a Breakpoint Instruction BKPT to the processor core on a match so providing hardware breakpoint...

Страница 196: ...ug Port The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences Once the mode has been changed unused debug pins can be reassig...

Страница 197: ...ire Data Pull up JTAG_TCLK SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull down JTAG_TDI I JTAG Test Data Input Pull up JTAG_TDO TRACE_SWO O JTAG Test Data Output O Trace output over...

Страница 198: ...G DP documentation for more information on these instructions Reserved 1 All other opcodes Decoded to select bypass register 1 The manufacturer reserves the right to change the decoding of reserved in...

Страница 199: ...MDM AP SELECT 7 4 0x0 selects the bank with Status and Ctrl A 3 2 2 b00 selects the Status Register A 3 2 2 b01 selects the Control Register SELECT 7 4 0xF selects the bank with IDR A 3 2 2 b11 select...

Страница 200: ...GREQ N Set to configure the system to be held in reset after the next recovery from a VLLSx mode This bit holds the in reset when VLLSx modes are exited to allow the debugger time to re initialize deb...

Страница 201: ...control logic has started the mass erase operation When mass erase is disabled via MEEN and SEC settings an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged 1 Flash...

Страница 202: ...bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS VLLSx Status Acknowledge bit in MDM AP Control register 10 VLLSx Modes Exit T...

Страница 203: ...HB AP supported sideband signal called HABORT This signal is driven into the Bus Matrix which resets the Bus Matrix state so that AHB AP can access the Private Peripheral Bus for last ditch debugging...

Страница 204: ...routing to the TPIU This configuration enables the use of trace with low cost tools while maintaining the compatibility with trace probes 9 10 TPIU The TPIU acts as a bridge between the on chip trace...

Страница 205: ...un to support core register access In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar With debug e...

Страница 206: ...FF FF OFF static OFF ITM FF FF FF OFF static OFF TPIU FF FF FF OFF static OFF DWT FF FF FF OFF static OFF 9 13 Debug Security When security is enabled FSEC SEC 10 the debug port capabilities are limi...

Страница 207: ...2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device For a comprehensive description of the module itself see the module s dedicated chapter Register...

Страница 208: ...Yes Yes Yes Yes Yes Pull enable at reset PTA0 PTA1 PTA2 PTA3 PTA4 Enabled Others Disabled Disabled Disabled Disabled Disabled Slew rate enable control Yes Yes Yes Yes Yes Slew rate enable at reset Di...

Страница 209: ...ke sure to disable the module For more details refer to the clock distribution chapter 10 2 3 Signal multiplexing constraints 1 A given peripheral function must be assigned to a maximum of one package...

Страница 210: ...B0_DM G1 12 7 E2 VOUT33 VOUT33 VOUT33 G2 13 8 D2 VREGIN VREGIN VREGIN H1 14 ADC0_DP1 ADC0_DP1 ADC0_DP1 H2 15 ADC0_DM1 ADC0_DM1 ADC0_DM1 J1 16 ADC1_DP1 ADC0_DP2 ADC1_DP1 ADC0_DP2 ADC1_DP1 ADC0_DP2 J2 1...

Страница 211: ...JTAG_TMS SWD_DIO PTA3 UART0_ RTS_b FTM0_CH0 JTAG_TMS SWD_DIO J8 38 26 G5 PTA4 LLWU_P3 NMI_b EZP_CS_b PTA4 LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b K7 39 27 F5 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 I2S0_TX_ BCL...

Страница 212: ...TB16 SPI1_SOUT UART0_RX FTM_ CLKIN0 EWM_IN E9 63 40 D7 PTB17 DISABLED PTB17 SPI1_SIN UART0_TX FTM_ CLKIN1 EWM_OUT_ b D9 64 41 D6 PTB18 DISABLED PTB18 FTM2_CH0 I2S0_TX_ BCLK FTM2_QD_ PHA C9 65 42 C7 PT...

Страница 213: ...SABLED PTC16 LPUART0_ RX C4 91 PTC17 DISABLED PTC17 LPUART0_ TX B4 92 PTC18 DISABLED PTC18 LPUART0_ RTS_b A4 PTC19 DISABLED PTC19 LPUART0_ CTS_b D4 93 57 C3 PTD0 LLWU_P12 DISABLED PTD0 LLWU_P12 SPI0_P...

Страница 214: ...NC NC NC H3 NC NC NC J9 NC NC NC J4 NC NC NC A10 NC NC NC A9 NC NC NC B1 NC NC NC C2 NC NC NC 10 3 2 K22F Pinouts The following figure shows the pinout diagram for the devices supported by this docume...

Страница 215: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 PTD7 PTD6 LLWU_P15 PTD5 PTD4 LLWU_P14 PTD3 PTD2 LLWU_P13 PTD1 PTD0 LLWU_P12 PTC11 LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4...

Страница 216: ...WU_P12 PTA0 VSS VSSA VREFL 3 XTAL32 4 PTD1 PTC10 VSS PTA1 VDD VDDA VREFH 4 EXTAL32 5 PTC11 LLWU_P11 PTC9 VDD PTA3 PTA2 PTA5 PTA4 LLWU_P3 5 VBAT 6 PTC8 PTC7 PTC1 LLWU_P6 PTB18 PTB16 PTB1 PTA13 LLWU_P4...

Страница 217: ...0_DM3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 PTD6 LLWU_P15 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8 50 49 48 47 46 45 44 43 42 41 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13 L...

Страница 218: ...LKOUT32K PTA0 VBAT 6 VSS 7 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 VDD VSS VSS PTE4 LLWU_P2 PTA2 PTA5 7 RTC_ WAKEUP_B 8 PTC4 LLWU_P8 PTC3 LLWU_P7 PTC2 PTC1 LLWU_P6 PTB23 PTB22 PTB3 PTA1 PTA4 LLWU_P3 PTA1...

Страница 219: ...G_TCLK SWD_CLK Serial Wire Clock I Table 10 5 TPIU Signal Descriptions Chip signal name Module signal name Description I O TRACE_SWO JTAG_TDO TRACE_SWO Trace output data from the ARM CoreSight debug b...

Страница 220: ...O EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q EzPort Serial Data Out Output 10 4 5 Analog Table 10 10 ADC 0 Signal D...

Страница 221: ...e Module signal name Description I O CMP0_IN 5 0 IN 5 0 Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10 13 CMP 1 Signal Descriptions Chip signal name Module signal name Description...

Страница 222: ...ase B input Input pin associated with quadrature decoder phase B I Table 10 18 FTM 2 Signal Descriptions Chip signal name Module signal name Description I O FTM_CLKIN 1 0 EXTCLK External clock FTM ext...

Страница 223: ...UT USB start of frame signal Can be used to make the USB start of frame available for external synchronization O Table 10 23 USB VREG Signal Descriptions Chip signal name Module signal name Descriptio...

Страница 224: ...tem I O Table 10 27 I2C 1 Signal Descriptions Chip signal name Module signal name Description I O I2C1_SCL SCL Bidirectional serial clock line of the I2C system I O I2C1_SDA SDA Bidirectional serial d...

Страница 225: ...generated I O I2S0_RX_FS SAI_RX_SYNC Receive Frame Sync The frame sync is an input sampled synchronously by the bit clock when externally generated and an output generated synchronously by the bit cl...

Страница 226: ...tput I O PTC 31 0 1 PORTC31 PORTC0 General purpose input output I O PTD 31 0 1 PORTD31 PORTD0 General purpose input output I O PTE 31 0 1 PORTE31 PORTE0 General purpose input output I O 1 The availabl...

Страница 227: ...its pin muxing state There is one instance of the PORT module for each port Not all pins within each port are implemented on a specific device 11 2 1 Features The PORT module has the following featur...

Страница 228: ...output Individual mux control field supporting analog or pin disabled GPIO and up to six chip specific digital functions Pad configuration fields are functional in all digital pin muxing modes 11 2 2...

Страница 229: ...face detailed signal description Signal I O Description PORTx 31 0 I O External interrupt State meaning Asserted pin is logic 1 Negated pin is logic 0 Timing Assertion may occur at any time and can as...

Страница 230: ...5 1 236 4004_9044 Pin Control Register n PORTA_PCR17 32 R W See section 11 5 1 236 4004_9048 Pin Control Register n PORTA_PCR18 32 R W See section 11 5 1 236 4004_904C Pin Control Register n PORTA_PC...

Страница 231: ...038 Pin Control Register n PORTB_PCR14 32 R W See section 11 5 1 236 4004_A03C Pin Control Register n PORTB_PCR15 32 R W See section 11 5 1 236 4004_A040 Pin Control Register n PORTB_PCR16 32 R W See...

Страница 232: ...See section 11 5 1 236 4004_B030 Pin Control Register n PORTC_PCR12 32 R W See section 11 5 1 236 4004_B034 Pin Control Register n PORTC_PCR13 32 R W See section 11 5 1 236 4004_B038 Pin Control Regis...

Страница 233: ...4 Pin Control Register n PORTD_PCR9 32 R W See section 11 5 1 236 4004_C028 Pin Control Register n PORTD_PCR10 32 R W See section 11 5 1 236 4004_C02C Pin Control Register n PORTD_PCR11 32 R W See sec...

Страница 234: ...4004_D018 Pin Control Register n PORTE_PCR6 32 R W See section 11 5 1 236 4004_D01C Pin Control Register n PORTE_PCR7 32 R W See section 11 5 1 236 4004_D020 Pin Control Register n PORTE_PCR8 32 R W S...

Страница 235: ...See section 11 5 1 236 4004_D07C Pin Control Register n PORTE_PCR31 32 R W See section 11 5 1 236 4004_D080 Global Pin Control Low Register PORTE_GPCLR 32 W always reads 0 0000_0000h 11 5 2 238 4004_D...

Страница 236: ...ptions chapter for reset values per port DSE field Varies by port See the Signal Multiplexing and Signal Descriptions chapter for reset values per port PFE field Varies by port See Signal Multiplexing...

Страница 237: ...falling edge 1011 Interrupt on either edge 1100 Interrupt when logic 1 Others Reserved 15 LK Lock Register 0 Pin Control Register fields 15 0 are not locked 1 Pin Control Register fields 15 0 are loc...

Страница 238: ...n muxing modes 0 Fast slew rate is configured on the corresponding pin if the pin is configured as a digital output 1 Slow slew rate is configured on the corresponding pin if the pin is configured as...

Страница 239: ...dress 84h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx...

Страница 240: ...flag will be cleared automatically at the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a level sensitive...

Страница 241: ...7 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFCR field descriptions Fi...

Страница 242: ...ional description 11 6 1 Pin control Each port pin has a corresponding Pin Control register PORT_PCRn associated with it The upper half of the Pin Control register configures the pin s capability to e...

Страница 243: ...ementing an external pull resistor will ensure a pin does not float when its input buffer is enabled note that the internal pull resistor is automatically disabled whenever the output buffer is enable...

Страница 244: ...e interrupt status flag is set for any enabled DMA request in that port The DMA request negates after the DMA transfer is completed because that clears the interrupt status flags for all enabled DMA r...

Страница 245: ...clock either the bus clock or the 1 kHz LPO clock If the synchronized input and the output of the digital filter remain different for a number of filter clock cycles equal to the filter width register...

Страница 246: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 246 Freescale Semiconductor Inc...

Страница 247: ...isters 12 1 1 Features Features of the SIM include System clocking configuration System clock divide values Architectural clock gating control USB clock selection and divide values Flash and system RA...

Страница 248: ...Device Identification Register SIM_SDID 32 R See section 12 2 8 262 4004_8034 System Clock Gating Control Register 4 SIM_SCGC4 32 R W F010_0030h 12 2 9 264 4004_8038 System Clock Gating Control Regist...

Страница 249: ...during System Reset from Flash IFR x Undefined at reset SIM_SOPT1 field descriptions Field Description 31 USBREGEN USB voltage regulator enable Controls whether the USB voltage regulator is enabled 0...

Страница 250: ...his field is reset only on POR LVD 00 System oscillator OSC32KCLK 01 Reserved 10 RTC 32 768kHz oscillator 11 LPO 1 kHz 17 16 OSC32KOUT 32K Oscillator Clock Output Outputs the ERCLK32K on the selected...

Страница 251: ...ows the SOPT1 USBSSTBY bit to be written This register bit clears after a write to USBSSTBY 0 SOPT1 USBSSTBY cannot be written 1 SOPT1 USBSSTBY can be written 25 UVSWE USB voltage regulator VLP standb...

Страница 252: ...04_7000h base 1004h offset 4004_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 LPUARTSRC 0 0 0 USBSRC PLLFLLSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5...

Страница 253: ...h frequency clock for various peripheral clocking options 00 MCGFLLCLK clock 01 MCGPLLCLK clock 10 Reserved 11 IRC48 MHz clock 15 13 Reserved This field is reserved This read only field is reserved an...

Страница 254: ...CLKSEL 0 FTM2CH1SRC FTM2CH0SRC FTM1CH0SRC 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FTM2FLT0 0 FTM1FLT0 0 0 FTM0FLT1 FTM0FLT0 W Reset 0 0 0 0 0 0 0 0 0 0...

Страница 255: ...1 FTM_CLK1 pin 24 FTM0CLKSEL FlexTimer 0 External Clock Pin Select Selects the external pin used to drive the clock to the FTM0 module NOTE The selected pin must also be configured for the FTM extern...

Страница 256: ...ion through the appropriate pin control register in the port control module 0 FTM1_FLT0 pin 1 CMP0 out 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 R...

Страница 257: ...Reserved This field is reserved This read only field is reserved and always has the value 0 15 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 6 UART1RX...

Страница 258: ...7 6 5 4 3 2 1 0 R ADC1ALTTRGE N 0 ADC1PRETRGS EL ADC1TRGSEL ADC0ALTTRGE N 0 ADC0PRETRGS EL ADC0TRGSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT7 field descriptions Field Description 31 16 Rese...

Страница 259: ...r timer LPTMR trigger 1111 Reserved 7 ADC0ALTTRGEN ADC0 alternate trigger enable Enable alternative conversion triggers for ADC0 0 PDB trigger selected for ADC0 1 Alternate trigger selected for ADC0 6...

Страница 260: ...10 9 8 7 6 5 4 3 2 1 0 R 0 0 FTM2SYNCBIT FTM1SYNCBIT FTM0SYNCBIT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT8 field descriptions Field Description 31 24 Reserved This field is reserved This read...

Страница 261: ...nel 1 output modulated by FTM1 channel 1 output 16 FTM0OCH0SRC FTM0 channel 0 output source 0 FTM0_CH0 pin is output of FTM0 channel 0 output 1 FTM0_CH0 pin is output of FTM0 channel 0 output modulate...

Страница 262: ...7x Family 27 24 SUBFAMID Kinetis Sub Family ID Specifies the Kinetis sub family of the device 0000 Kx0 Subfamily 0001 Kx1 Subfamily tamper detect 0010 Kx2 Subfamily 0011 Kx3 Subfamily tamper detect 01...

Страница 263: ...er 010 K3x Family or K1x K6x Family with tamper 011 K4x Family or K2x Family with tamper 100 K6x Family without tamper 101 K7x Family 110 Reserved 111 Reserved 3 0 PINID Pincount identification Specif...

Страница 264: ...0 20 VREF VREF Clock Gate Control This bit controls the clock gate to the VREF module 0 Clock disabled 1 Clock enabled 19 CMP Comparator Clock Gate Control This bit controls the clock gate to the com...

Страница 265: ...enabled 6 I2C0 I2C0 Clock Gate Control This bit controls the clock gate to the I 2 C0 module 0 Clock disabled 1 Clock enabled 5 4 Reserved This field is reserved This read only field is reserved and a...

Страница 266: ...is reserved and always has the value 1 17 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 PORTE Port E Clock Gate Control This bit controls the clock...

Страница 267: ...is reserved This read only field is reserved and always has the value 0 1 Reserved This field is reserved This read only field is reserved and always has the value 1 0 LPTMR Low Power Timer Access Con...

Страница 268: ...s the clock gate to the ADC0 module 0 Clock disabled 1 Clock enabled 26 FTM2 FTM2 Clock Gate Control This bit controls the clock gate to the FTM2 module 0 Clock disabled 1 Clock enabled 25 FTM1 FTM1 C...

Страница 269: ...ays has the value 0 13 SPI1 SPI1 Clock Gate Control This bit controls the clock gate to the SPI1 module 0 Clock disabled 1 Clock enabled 12 SPI0 SPI0 Clock Gate Control This bit controls the clock gat...

Страница 270: ...orted while the flash memory is clock gated but entry into low power modes and HSRUN mode is blocked 0 Clock disabled 1 Clock enabled 12 2 12 System Clock Gating Control Register 7 SIM_SCGC7 Address 4...

Страница 271: ...E The CLKDIV1 register cannot be written to when the device is in VLPR mode Address 4004_7000h base 1044h offset 4004_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Страница 272: ...de by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 23 20 Reserved This field is reserved This read o...

Страница 273: ...0 SIM_CLKDIV2 field descriptions Field Description 31 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 1 USBDIV USB clock divider divisor This field sets...

Страница 274: ...IM_FCFG1 field descriptions Field Description 31 28 Reserved This field is reserved This read only field is reserved and always has the value 0 27 24 PFSIZE Program flash size This field specifies the...

Страница 275: ...sabled for the duration of Wait mode An attempt by the DMA or other bus master to access the Flash when the Flash is disabled will result in a bus error This bit should be clear during VLP modes The F...

Страница 276: ...example if MAXADDR0 0x20 the first invalid address of flash block 0 is 0x0004_0000 This would be the MAXADDR0 value for a device with 256 KB program flash in flash block 0 23 Reserved This field is r...

Страница 277: ...Unique identification for the device 12 2 18 Unique Identification Register Mid High SIM_UIDMH Address 4004_7000h base 1058h offset 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Страница 278: ...12 2 20 Unique Identification Register Low SIM_UIDL Address 4004_7000h base 1060h offset 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W Re...

Страница 279: ...do not have an on chip ROM are shipped with the pre programmed Kinetis Flashloader in the on chip flash memory for one time in system factory programming The Kinetis Flashloader s main task is to load...

Страница 280: ...peripherals Packet error detection and retransmission Fully supports flash security including ability to mass erase or unlock security via the backdoor key Protection of RAM used by the flashloader w...

Страница 281: ...t the chip SetProperty Attempt to modify a writable property Supported 13 3 Functional Description The following sub sections describe the Kinetis Flashloader functionality 13 3 1 Memory Maps While ex...

Страница 282: ...ed peripherals are initialized 3 The flashloader waits for communication to begin on a peripheral There is no timeout for the active peripheral detection process If communication is detected then all...

Страница 283: ...s Was a Init UART1 SPI1 and I2C1 SPI1 entered interrupt state Has No activity detected on USB No Was Yes Figure 13 2 Kinetis Flashloader Start up Flowchart 13 3 4 Clock Configuration The Kinetis Flash...

Страница 284: ...data phase is incoming from host to flashloader then it the data phase is part of the original command If the data phase is outgoing from flashloader to host then it the data phase is part of the res...

Страница 285: ...al Response ACK Data packet ACK Process data Final data packet ACK Final Response ACK Process data Figure 13 4 Command with incoming data phase NOTE The host may not send any further packets while it...

Страница 286: ...y sending a zero length data packet The final Generic Response packet sent after the data phase includes the status for the entire operation 13 3 5 3 Command with outgoing data phase The protocol for...

Страница 287: ...the data phase is really considered part of the response command The host may not send any further packets while it the host is waiting for the response to a command If the ReadMemory Response command...

Страница 288: ...get is packetized NOTE The term target refers to the Kinetis Flashloader device There are 6 types of packets used in device Ping packet Ping Response packet Framing packet Command packet Data packet R...

Страница 289: ...ermine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host starts sending commands to the targe...

Страница 290: ...tType 2 length_low Length is a 16 bit field that specifies the entire command or data packet size in bytes 3 length_high 4 crc16_low This is a 16 bit field The CRC16 value covers entire framing packet...

Страница 291: ...mingPacketType_AckAbort Data phase is being aborted 0xA4 kFramingPacketType_Command The framing packet contains a command packet payload 0xA5 kFramingPacketType_Data The framing packet contains a data...

Страница 292: ...command packet is 32 bytes long only 7 parameters can fit into the command packet Command packets are also used by the target to send responses back to the host As mentioned earlier command packets an...

Страница 293: ...length 32 bits With the default maximum packet size of 32 bytes a command packet can contain up to 7 parameters 13 3 6 5 Data packet The data packet carries just the data either host sending data to t...

Страница 294: ...The Command tag parameter identifies the response to the command sent by the host GetPropertyResponse The GetPropertyResponse packet is sent by the target in response to the host query that uses the...

Страница 295: ...ckets shown in this section Please refer to the HID reports section for details of the USB HID packet structure 13 3 7 1 GetProperty command The GetProperty command is used to query the flashloader ab...

Страница 296: ...Type_Command length 0x08 0x00 crc16 0x73 0xD4 Command packet commandTag 0x07 GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 CurrentVersion The GetProperty command has...

Страница 297: ...the values of the properties or options in the Kinetis Flashloader However the SetProperty command can only change the value of properties that are writable see Table 13 43 Properties used by Get SetP...

Страница 298: ...cketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A VerifyWrites prope...

Страница 299: ...in the commandTag field of the command packet The FlashEraseAll command requires no parameters Process command Host Target FlashEraseAll 0x5a a4 04 00c4 2e 01 00 00 00 0x5a a4 0c 00 53 63 a0 00 04 02...

Страница 300: ...Region command will fail and return kStatus_FlashAddressError 102 If any part of the region specified is protected the FlashEraseRegion command will fail and return kStatus_MemoryRangeInvalid 10200 Ta...

Страница 301: ...ill with a byte pattern 8 bit the byte must be replicated 4 times in the pattern word To fill with a short pattern 16 bit the short value must be replicated 2 times in the pattern word For example to...

Страница 302: ...us code 13 3 7 6 FlashProgramOnce command The FlashProgramOnce command writes data that is provided in a command packet to a specified range of bytes in the program once field Special care must be tak...

Страница 303: ...th 0x10 0x00 crc16 0x7E4 0x89 Command packet commandTag 0x0E FlashProgramOnce flags 0 reserved 0 parameterCount 3 index 0x0000_0000 byteCount 0x0000_0004 data 0x1234_5678 Response upon successful exec...

Страница 304: ...0 00 04 00 00 00 0x5a a4 10 00 3f 6f af 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 Figure 13 12 Protocol Sequence for FlashReadOnce Command Table 13 30 FlashReadOnce Command Packet Format Example Fl...

Страница 305: ...e Field upon successful execution of the command or will return with a status code set to an appropriate error status code and a byte count set to 0 13 3 7 8 FlashReadResource command The FlashReadRes...

Страница 306: ...00 06 5a a4 0c 00 75 a3 a0 00 00 02 00 00 00 00 10 00 00 00 Figure 13 13 Protocol Sequence for FlashReadResource Command Table 13 33 FlashReadResource Command Packet Format Example FlashReadResource...

Страница 307: ...ied range of bytes in memory flash or RAM However if flash protection is enabled then writes to protected sectors will fail Special care must be taken when writing to flash First any flash sector writ...

Страница 308: ...0c 00 27 1f a0 00ff 02 00 00 00 00 04 00 00 00 ACK 0x5a a1 ACK 0x5a a1 Data packet 0x5a a5 20 00 CRC16 32bytes data Process Data ACK 0x5a a1 Final Data packet 0x5a a5 length16 CRC16 32 bytes data ACK...

Страница 309: ...return a GenericResponse packet with a status code set to kStatus_Success upon successful execution of the command or to an appropriate error status code 13 3 7 10 Read memory command The ReadMemory...

Страница 310: ...eserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 Data Phase The ReadMemory command has a data phase Since the target Kinetis Flashloader works in slave mode the host need...

Страница 311: ...command Table 13 39 Parameters for FlashSecurityDisable Command Byte Command 0 3 Backdoor key low word 4 7 Backdoor key high word Process command Host Target FlashSecureDisable with backdoor key 01020...

Страница 312: ...the program counter to the code at the provided jump address R0 to the provided argument and a Stack pointer to the provided stack pointer address Prior to the jump the system is returned to the reset...

Страница 313: ...at Example Reset Parameter Value Framing packet start byte 0x5A packetType 0xA4 kFramingPacketType_Command length 0x04 0x00 crc16 0x6F 0x46 Command packet commandTag 0x0B reset flags 0x00 reserved 0x0...

Страница 314: ...loader Peripheral Pinmux Upon exit from the flashloader the flashloader leaves global interrupts disabled and restores the VTOR register to its default value 0x0 NOTE PORT clock gate pin mux and perip...

Страница 315: ...n incoming packet is sent by the host with a selected I2C slave address and the direction bit is set as write An outgoing packet is read by the host with a selected I2C slave address and the direction...

Страница 316: ...than supported length Yes payload data from target No Set payload length to maximum supported length No No Reached maximum Report a timeout Yes End No 2 bytes Read 1 byte from target 0x5A received 0xA...

Страница 317: ...x00 will be sent as response to host if target is under the following conditions Processing incoming packet Preparing outgoing data Received invalid data The following flowcharts demonstrate how the h...

Страница 318: ...out payload data from target No Set payload length to maximum supported length No No maximum Report a timeout error End Yes End No 2 bytes 0x5A received 0xA4 received Reached retries Send 0x00 to shi...

Страница 319: ...uously with no delay between bytes in a fixed UART transmission mode 8 bit data no parity bit and 1 stop bit If the bytes of the ping packet are sent one by one with some delay between them the autoba...

Страница 320: ...retries Figure 13 24 Host reads an ACK from target via UART Wait for ping response Yes Yes End Report Error No No Wait for 1 byte from target Wait for 1 byte from target 0x5A received 0xA7 received W...

Страница 321: ...g packets instead the packetization inherent in the USB protocol itself is used The ability for the device to NAK Out transfers until they can be received provides the required flow control the built...

Страница 322: ...d requests from the USB host 13 4 4 4 HID reports There are 4 HID reports defined and used by the flashloader USB HID peripheral The report ID determines the direction and type of packet sent in the r...

Страница 323: ...e endian format and it is set to the size in bytes of the packet sent in the report This size does not include the Report ID or the Packet Length header itself During a data phase a packet size of 0 i...

Страница 324: ...ontrols whether the flashloader will validate attempts to write to memory regions i e check if they are reserved before attempting to write ValidateRegions feature is enabled by default 0 No validatio...

Страница 325: ...f the peripheral is available then the corresponding bit will be set in the property value All reserved bits must be set to 0 13 5 1 3 AvailableCommands Property This property value is a bitfield with...

Страница 326: ...ss or length is outside addressable memory kStatus_ FlashAccessError 103 The FTFA_FSTAT ACCERR bit is set kStatus_FlashProtectionViolation 104 The FTFA_FSTAT FPVIOL bit is set kStatus_ FlashCommandFai...

Страница 327: ...10200 Memory range conflicts with a protected region kStatus_UnknownProperty 10300 The requested property value is undefined kStatus_ReadOnlyProperty 10301 The requested property value cannot be writ...

Страница 328: ...Kinetis Flashloader Status Error Codes K22F Sub Family Reference Manual Rev 3 7 2014 328 Freescale Semiconductor Inc...

Страница 329: ...provide reset status information and reset filter control NOTE The RCM registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus error RCM memor...

Страница 330: ...1 Other reset a bit is set if its corresponding reset source caused the reset Address 4007_F000h base 0h offset 4007_F000h Bit 7 6 5 4 3 2 1 0 Read POR PIN WDOG 0 LOL LOC LVD WAKEUP Write Reset 1 0 0...

Страница 331: ...1 Reset caused by a loss of external clock 1 LVD Low Voltage Detect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs This field is also set by POR...

Страница 332: ...ESET command while the device is in EzPort mode 0 Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode 1 Reset caused by EzPort receiving the RESET command while t...

Страница 333: ...0 0 RCM_RPFC field descriptions Field Description 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 RSTFLTSS Reset Pin Filter Select in Stop Mode Select...

Страница 334: ...ilter count is 5 00101 Bus clock filter count is 6 00110 Bus clock filter count is 7 00111 Bus clock filter count is 8 01000 Bus clock filter count is 9 01001 Bus clock filter count is 10 01010 Bus cl...

Страница 335: ...g the last Chip Reset Address 4007_F000h base 7h offset 4007_F007h Bit 7 6 5 4 3 2 1 0 Read 0 EZP_MS 0 Write Reset 0 0 0 0 0 0 0 0 RCM_MR field descriptions Field Description 7 2 Reserved This field i...

Страница 336: ...used by POR 1 Reset caused by POR 6 SPIN Sticky External Reset Pin Indicates a reset has been caused by an active low level on the external RESET pin 0 Reset not caused by external reset pin 1 Reset c...

Страница 337: ...his reset Any enabled wakeup source in a VLLSx mode causes a reset 0 Reset not caused by LLWU module wakeup source 1 Reset caused by LLWU module wakeup source 14 2 7 Sticky System Reset Status Registe...

Страница 338: ...ger system setting of the System Reset Request bit in the MDM AP Control Register 0 Reset not caused by host debugger system setting of the System Reset Request bit 1 Reset caused by host debugger sys...

Страница 339: ...that mode This chapter describes all the available low power modes the sequence followed to enter exit each mode and the functionality available while in each of the modes The SMC is able to function...

Страница 340: ...variety of stop modes are available that allow the state retention partial power down or full power down of certain logic and or memory I O states are held in all modes of operation Several registers...

Страница 341: ...from supporting peripherals are valid The MCU is placed in a low leakage mode by powering down the internal logic and the system RAM2 partition The system RAM1 partition contents are retained in this...

Страница 342: ...ry into any low power run or stop mode The enabling of the low power run or stop mode occurs by configuring the Power Mode Control register PMCTRL The PMPROT register can be written only once after an...

Страница 343: ...allows the MCU to enter any low leakage stop mode LLS 0 Any LLSx mode is not allowed 1 Any LLSx mode is allowed 2 Reserved This field is reserved This read only field is reserved and always has the va...

Страница 344: ...s read only field is reserved and always has the value 0 3 STOPA Stop Aborted When set this read only status bit indicates an interrupt occured during the previous stop mode entry sequence preventing...

Страница 345: ...0 0 1 1 SMC_STOPCTRL field descriptions Field Description 7 6 PSTOPO Partial Stop Option These bits control whether a Partial Stop mode is entered when STOPM STOP When entering a Partial Stop mode fr...

Страница 346: ...LSx 011 VLLS3 if PMCTRL STOPM VLLSx LLS3 if PMCTRL STOPM LLSx 100 Reserved 101 Reserved 110 Reserved 111 Reserved 15 3 4 Power Mode Status register SMC_PMSTAT PMSTAT is a read only one hot register wh...

Страница 347: ...is VLPW 0001_0000 Current power mode is VLPS 0010_0000 Current power mode is LLS 0100_0000 Current power mode is VLLS 1000_0000 Current power mode is HSRUN 15 4 Functional description 15 4 1 Power mo...

Страница 348: ...the previous figure Table 15 7 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Contr...

Страница 349: ...hich is controlled in System Control Register in ARM core See note 1 VLPS VLPR Interrupt NOTE If VLPS was entered directly from RUN transition 7 hardware forces exit back to RUN and does not allow a t...

Страница 350: ...1 or 10 then only a Partial Stop mode is entered instead of STOP 3 If PMCTRL STOPM 000 and STOPCTRL PSTOPO 00 then VLPS mode is entered instead of STOP If PMCTRL STOPM 000 and STOPCTRL PSTOPO 01 or 10...

Страница 351: ...es 4 The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low power stop mode 15 4 2 3 Aborted stop mode entry If an interrupt occurs during a...

Страница 352: ...the start PC from vector table offset 0x004 LR is set to 0xFFFF_FFFF To reduce power in this mode disable the clocks to unused modules using their corresponding clock gating control bits in the SIM s...

Страница 353: ...a higher execution frequency is desired poll PMSTAT until it is set to RUN when returning from VLPR mode Any reset always causes an exit from VLPR and returns the device to RUN mode after the MCU exi...

Страница 354: ...est occurs the CPU exits WAIT mode and resumes processing in RUN mode beginning with the stacking operations leading to the interrupt service routine A system reset will cause an exit from WAIT mode r...

Страница 355: ...may be traded off NOTE All clock monitors must be disabled before entering these low power modes Stop VLPS VLPR VLPW LLS and VLLSx The various stop modes are selected by setting the appropriate fields...

Страница 356: ...in normal RUN mode and PMCTRL STOPM 010 When VLPS is entered directly from RUN mode exit to VLPR is disabled by hardware and the system will always exit back to RUN In VLPS the on chip voltage regula...

Страница 357: ...xiting via the RESET pin RCM_SRS0 PIN and RCM_SRS0 WAKEUP are set 15 4 5 4 Very Low Leakage Stop VLLSx modes This device contains these very low leakage modes VLLS3 VLLS2 VLLS1 VLLS0 VLLSx is often us...

Страница 358: ...ves a corresponding acknowledge for each signal that is both CDBGPWRUPACK and CSYSPWRUPACK When both requests are asserted the mode controller handles attempts to enter STOP and VLPS by entering an em...

Страница 359: ...ebug IP and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin The VLLDBGACK bit is cleared by the debugger or can be left set...

Страница 360: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 360 Freescale Semiconductor Inc...

Страница 361: ...voltage regulator Active POR providing brown out detect Low voltage detect supporting two low voltage trip points with four warning levels per trip point 16 3 Low voltage detect LVD system This devic...

Страница 362: ...voltage condition The low voltage detection threshold is determined by LVDSC1 LVDV After an LVD reset occurs the LVD system holds the MCU in reset until the supply voltage rises above this threshold T...

Страница 363: ...in the I O are released and default to their reset state In this case no write to REGSC ACKISO is needed 16 5 Memory map and register descriptions Details about the PMC registers can be found here NOT...

Страница 364: ...systems that must have LVD always on configure the Power Mode Protection PMPROT register of the SMC module SMC_PMPROT to disallow any very low power or low leakage modes from being enabled See the dev...

Страница 365: ...e 0 1 0 LVDV Low Voltage Detect Voltage Select Selects the LVD trip point voltage V LVD 00 Low trip point selected V LVD V LVDL 01 High trip point selected V LVD V LVDH 10 Reserved 11 Reserved 16 5 2...

Страница 366: ...Enables hardware interrupt requests for LVWF 0 Hardware interrupt disabled use polling 1 Request a hardware interrupt when LVWF 1 4 2 Reserved This field is reserved This read only field is reserved...

Страница 367: ...in VLPx LLS and VLLSx modes 1 Bandgap voltage reference is enabled in VLPx LLS and VLLSx modes 3 ACKISO Acknowledge Isolation Reading this field indicates whether certain peripherals and the I O pads...

Страница 368: ...eld Description 0 BGBE Bandgap Buffer Enable Enables the bandgap buffer 0 Bandgap buffer not enabled 1 Bandgap buffer enabled Memory map and register descriptions K22F Sub Family Reference Manual Rev...

Страница 369: ...o exit both LLS and VLLS through a reset flow The LLWU module also includes two optional digital pin filters for the external wakeup pins See AN4503 Power Management for Kinetis and ColdFire MCUs for...

Страница 370: ...interrupt flow when exiting LLS NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery 17 1 2 2 V...

Страница 371: ...leakge mode interrupt flow reset flow LLWU_P0 LLWU_P15 Pin filter 1 wakeup occurred Interrupt module flag detect WUPE15 2 Edge detect enter low leakge mode WUPE0 Edge detect Module7 interrupt flag LLW...

Страница 372: ...that caused exit from a low leakage power mode includes external pin or internal module interrupt Wake up pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode Wri...

Страница 373: ...ct the edge detect type for the external wakeup input pins LLWU_P3 LLWU_P0 NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected by re...

Страница 374: ...l input pin enabled with falling edge detection 11 External input pin enabled with any change detection 17 3 2 LLWU Pin Enable 2 register LLWU_PE2 LLWU_PE2 contains the field to enable and select the...

Страница 375: ...ed with any change detection 1 0 WUPE4 Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin e...

Страница 376: ...sabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 1 0 WU...

Страница 377: ...keup Pin Enable For LLWU_P13 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 Ext...

Страница 378: ...le flag not used as wakeup source 1 Internal module flag used as wakeup source 4 WUME4 Wakeup Module Enable For Module 4 Enables an internal module as a wakeup source input 0 Internal module flag not...

Страница 379: ...ot VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected by reset types that do not trigger Chip Reset not VLLS See the Introduction details for more information Address 4007_C000h...

Страница 380: ...clear the flag write a 1 to WUF3 0 LLWU_P3 input was not a wake up source 1 LLWU_P3 input was a wake up source 2 WUF2 Wakeup Flag For LLWU_P2 Indicates that an enabled external wakeup pin was a sourc...

Страница 381: ...UF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field Description 7 WUF15 Wakeup Flag For LLWU_P15 Indicates that an enabled external wakeup pin was a s...

Страница 382: ...was a source of exiting a low leakage power mode To clear the flag write a 1 to WUF9 0 LLWU_P9 input was not a wakeup source 1 LLWU_P9 input was a wakeup source 0 WUF8 Wakeup Flag For LLWU_P8 Indicate...

Страница 383: ...Module 6 input was not a wakeup source 1 Module 6 input was a wakeup source 5 MWUF5 Wakeup flag For module 5 Indicates that an enabled internal peripheral was a source of exiting a low leakage power...

Страница 384: ...anism 0 Module 0 input was not a wakeup source 1 Module 0 input was a wakeup source 17 3 9 LLWU Pin Filter 1 register LLWU_FILT1 LLWU_FILT1 is a control and status register that is used to enable disa...

Страница 385: ...LWU_FILT2 is a control and status register that is used to enable disable the digital filter 2 features for an external pin NOTE This register is reset on Chip Reset not VLLS and by reset types that t...

Страница 386: ...operational only in LLS and VLLSx modes The LLWU module contains pin enables for each external pin and internal module For each external pin the user can disable or select the edge type for the wakeup...

Страница 387: ...a reset vector fetch 17 4 3 Initialization For an enabled peripheral wakeup input the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from the...

Страница 388: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 388 Freescale Semiconductor Inc...

Страница 389: ...on 18 2 Memory map register descriptions The memory map and register descriptions below describe the registers using byte addresses MCM memory map Absolute address hex Register name Width in bits Acce...

Страница 390: ...d descriptions Field Description 15 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 0 ASC Each bit in the ASC field indicates whether there is a corresp...

Страница 391: ...crossbar masters Address E008_0000h base Ch offset E008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Страница 392: ...the flags remain asserted until software clears the corresponding FPSCR bit Address E008_0000h base 10h offset E008_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R FIDCE 0 FIXCE FUFCE FOF...

Страница 393: ...the processor s FPU Once set this bit remains set until software clears the FPSCR IDC bit 0 No interrupt 1 Interrupt occurred 14 13 Reserved This field is reserved This read only field is reserved an...

Страница 394: ...ected in the processor s FPU Once set this bit remains set until software clears the FPSCR DZC bit 0 No interrupt 1 Interrupt occurred 8 FIOC FPU invalid operation interrupt status This read only bit...

Страница 395: ...nly field is reserved and always has the value 0 2 CPOWOI Compute Operation wakeup on interrupt 0 No effect 1 When set the CPOREQ is cleared on any interrupt or exception vector fetch 1 CPOACK Compute...

Страница 396: ...nabled FUFCE and an underflow occurs FUFC FPU overflow interrupt is enabled FOFCE and an overflow occurs FOFC FPU divide by zero interrupt is enabled FDZCE and a divide by zero occurs FDZC FPU invalid...

Страница 397: ...is structure allows up to four bus masters to access different bus slaves simultaneously while providing arbitration among the bus masters when they access the same slave 19 1 1 Features The crossbar...

Страница 398: ...of whether it actually owns the slave port it is targeting While the master does not have control of the slave port it is targeting it simply waits A master is given control of the targeted slave port...

Страница 399: ...xed priority operation When operating in fixed priority mode each master is assigned a unique priority level with the highest numbered master having the highest priority for example in a system with 5...

Страница 400: ...ber ID of the last master to perform a transfer on the slave bus The highest priority requesting master becomes owner of the slave bus at the next transfer boundary Priority is based on how far ahead...

Страница 401: ...AXBS section of the configuration chapter for the reset state of the arbitration scheme Chapter 19 Crossbar Switch Lite AXBS Lite K22F Sub Family Reference Manual Rev 3 7 2014 Freescale Semiconductor...

Страница 402: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 402 Freescale Semiconductor Inc...

Страница 403: ...assignments The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals 20 1 1 Features Key features of the peripheral bridge are Supports peripheral slot...

Страница 404: ...bar switch and the slave peripheral bus The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decodin...

Страница 405: ...of this module s instances see the chip configuration information 21 1 1 Overview The Direct Memory Access Multiplexer DMAMUX routes DMA sources called slots to any of the 16 DMA channels This proces...

Страница 406: ...ur always on slots can be routed to 16 channels 16 independently selectable DMA channel routers The first four channels additionally provide a trigger functionality Each channel router can be assigned...

Страница 407: ...UX has no external pins 21 3 Memory map register definition This section provides a detailed description of all memory mapped registers in the DMAMUX DMAMUX memory map Absolute address hex Register na...

Страница 408: ...slots peripheral slots or always on slots in the system NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior This is true even if a channel is disable...

Страница 409: ...nctionally the DMAMUX channels may be divided into two classes Channels that implement the normal routing functionality plus periodic triggering capability Channels that implement only the normal rout...

Страница 410: ...been seen This is illustrated in the following figure DMA request Peripheral request Trigger Figure 21 20 DMAMUX channel triggering normal operation After the DMA request has been serviced the periph...

Страница 411: ...hod to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO ports to drive or sample waveforms By configuring the DMA to tran...

Страница 412: ...e software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions of the m...

Страница 413: ...use 21 5 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 4 DMA channels have pe...

Страница 414: ...ing the channel 3 Write 0x85 to CHCFG1 base address 0x01 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following exampl...

Страница 415: ...le illustrates steps 2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMA...

Страница 416: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 416 Freescale Semiconductor Inc...

Страница 417: ...lex data transfers with minimal intervention from a host processor The hardware microarchitecture includes A DMA engine that performs Source and destination address calculations Data movement operatio...

Страница 418: ...Data Write Address Internal Peripheral Bus eDMA Peripheral Request eDMA Done Figure 22 1 eDMA system block diagram 22 1 2 Block parts The eDMA module is partitioned into two major modules the eDMA eng...

Страница 419: ...ata bus is the primary output The address and data path modules directly support the 2 stage pipelined internal bus The address path module represents the 1st stage of the bus pipeline address phase w...

Страница 420: ...sfer control descriptor TCD organized to support two deep nested transfer operations 32 byte TCD stored in local memory for each channel An inner data transfer loop defined by a minor byte transfer co...

Страница 421: ...mode via the control register If CR EDBG is cleared the DMA continues to operate If CR EDBG is set the eDMA stops transferring data If Debug mode is entered while a channel is active the eDMA continue...

Страница 422: ...ialization Prior to activating a channel you must initialize its TCD with the appropriate transfer profile Memory map register definition K22F Sub Family Reference Manual Rev 3 7 2014 422 Freescale Se...

Страница 423: ...9 8 7 6 5 4 3 2 1 0 CITER E_LINK CITER or CITER LINKCH CITER DOFF DLAST_SGA BITER E_LINK BITER or BITER LINKCH BITER START INT_MAJ INT_HALF D_REQ E_SG MAJOR E_LINK ACTIVE DONE BWC MAJOR LINKCH NBYTES...

Страница 424: ...Request Register DMA_SERQ 8 W always reads 0 00h 22 3 8 446 4000_801C Clear DONE Status Bit Register DMA_CDNE 8 W always reads 0 00h 22 3 9 447 4000_801D Set START Bit Register DMA_SSRT 8 W always re...

Страница 425: ...Loop Disabled DMA_TCD0_NBYTES_MLNO 32 R W Undefined 22 3 21 464 4000_9008 TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled DMA_TCD0_NBYTES_MLOFFNO 32 R W Undefined 22 3 22 465 4000_...

Страница 426: ...ink Major Loop Count Channel Linking Disabled DMA_TCD1_BITER_ELINKNO 16 R W Undefined 22 3 32 475 4000_9040 TCD Source Address DMA_TCD2_SADDR 32 R W Undefined 22 3 18 462 4000_9044 TCD Signed Source A...

Страница 427: ...bled DMA_TCD3_CITER_ELINKYES 16 R W Undefined 22 3 27 469 4000_9076 DMA_TCD3_CITER_ELINKNO 16 R W Undefined 22 3 28 470 4000_9078 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD...

Страница 428: ...65 4000_90A8 TCD Signed Minor Loop Offset Minor Loop and Offset Enabled DMA_TCD5_NBYTES_MLOFFYES 32 R W Undefined 22 3 23 466 4000_90AC TCD Last Source Address Adjustment DMA_TCD5_SLAST 32 R W Undefin...

Страница 429: ...s DMA_TCD7_SADDR 32 R W Undefined 22 3 18 462 4000_90E4 TCD Signed Source Address Offset DMA_TCD7_SOFF 16 R W Undefined 22 3 19 462 4000_90E6 TCD Transfer Attributes DMA_TCD7_ATTR 16 R W Undefined 22...

Страница 430: ...catter Gather Address DMA_TCD8_DLASTSGA 32 R W Undefined 22 3 29 471 4000_911C TCD Control and Status DMA_TCD8_CSR 16 R W Undefined 22 3 30 472 4000_911E TCD Beginning Minor Loop Link Major Loop Count...

Страница 431: ...R W Undefined 22 3 24 467 4000_9150 TCD Destination Address DMA_TCD10_DADDR 32 R W Undefined 22 3 25 468 4000_9154 TCD Signed Destination Address Offset DMA_TCD10_DOFF 16 R W Undefined 22 3 26 468 40...

Страница 432: ...Signed Source Address Offset DMA_TCD12_SOFF 16 R W Undefined 22 3 19 462 4000_9186 TCD Transfer Attributes DMA_TCD12_ATTR 16 R W Undefined 22 3 20 463 4000_9188 TCD Minor Byte Count Minor Loop Disabl...

Страница 433: ...28 470 4000_91B8 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD13_DLASTSGA 32 R W Undefined 22 3 29 471 4000_91BC TCD Control and Status DMA_TCD13_CSR 16 R W Undefined 22 3 30...

Страница 434: ...set Minor Loop Enabled and Offset Disabled DMA_TCD15_NBYTES_MLOFFNO 32 R W Undefined 22 3 22 465 4000_91E8 TCD Signed Minor Loop Offset Minor Loop and Offset Enabled DMA_TCD15_NBYTES_MLOFFYES 32 R W U...

Страница 435: ...offsets TCDn_SLAST and TCDn_DLAST_SGA are used to compute the next TCDn_SADDR and TCDn_DADDR values When minor loop mapping is enabled EMLM is 1 TCDn word2 is redefined A portion of TCDn word2 is used...

Страница 436: ...ly field is reserved and always has the value 0 7 EMLM Enable Minor Loop Mapping 0 Disabled TCDn word2 is defined as a 32 bit NBYTES field 1 Enabled TCDn word2 is redefined to include individual enabl...

Страница 437: ...ed channel error Channel errors can be caused by A configuration error that is An illegal setting in the transfer control descriptor or An illegal priority register setting in fixed arbitration An err...

Страница 438: ...rded error was a configuration error detected in the TCDn_SADDR field TCDn_SADDR is inconsistent with TCDn_ATTR SSIZE 6 SOE Source Offset Error 0 No source offset configuration error 1 The last record...

Страница 439: ...enable is directly affected by writes to this register it is also affected by writes to the SERQ and CERQ registers These registers are provided so the request enable for a single channel can easily...

Страница 440: ...is enabled 10 ERQ10 Enable DMA Request 10 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 9 ERQ9 Enable DMA Reques...

Страница 441: ...signal for the corresponding channel is enabled 22 3 4 Enable Error Interrupt Register DMA_EEI The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each ch...

Страница 442: ...al for corresponding channel generates an error interrupt request 11 EEI11 Enable Error Interrupt 11 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion o...

Страница 443: ...tes an error interrupt request 1 EEI1 Enable Error Interrupt 1 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding c...

Страница 444: ...the EEI to be set Setting the SAEE bit provides a global set function forcing the entire EEI contents to be set If the NOP bit is set the command is ignored This allows you to write multiple byte reg...

Страница 445: ...OP is set the command is ignored This allows you to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ah offset 4000_801Ah Bit 7 6 5 4 3...

Страница 446: ...registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Bh offset 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ fi...

Страница 447: ...t word Reads of this register return all zeroes Address 4000_8000h base 1Ch offset 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE field descriptions Fie...

Страница 448: ...eads of this register return all zeroes Address 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field Descr...

Страница 449: ...ple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0 0 0 0 0 0 DM...

Страница 450: ...u to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Fh offset 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0...

Страница 451: ...1 in any bit position clears the corresponding channel s interrupt request A zero in any bit position has no affect on the corresponding channel s current interrupt status The CINT register is provide...

Страница 452: ...eared 1 The interrupt request for corresponding channel is active 9 INT9 Interrupt Request 9 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding chan...

Страница 453: ...to the interrupt controller During the execution of the interrupt service routine associated with any DMA errors it is software s responsibility to clear the appropriate bit negating the error interr...

Страница 454: ...annel has not occurred 1 An error in this channel has occurred 14 ERR14 Error In Channel 14 0 An error in this channel has not occurred 1 An error in this channel has occurred 13 ERR13 Error In Channe...

Страница 455: ...channel has not occurred 1 An error in this channel has occurred 4 ERR4 Error In Channel 4 0 An error in this channel has not occurred 1 An error in this channel has occurred 3 ERR3 Error In Channel...

Страница 456: ...Therefore this status is affected by the ERQ bits Address 4000_8000h base 34h offset 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15...

Страница 457: ...the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardware 0 A hardware service request for channe...

Страница 458: ...request for channel 6 is not present 1 A hardware service request for channel 6 is present 5 HRS5 Hardware Request Status Channel 5 The HRS bit for its respective channel remains asserted for the per...

Страница 459: ...tive channel remains asserted for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardware 0 A h...

Страница 460: ...request for channel 10 1 Enable asynchronous DMA request for channel 10 9 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 0 Disable asynchronous DMA request for channel 9 1 Enable a...

Страница 461: ...ion is enabled CR ERCA 0 the contents of these registers define the unique priorities associated with each channel The channel priorities are evaluated by numeric value for example 0 is the lowest pri...

Страница 462: ...18 TCD Source Address DMA_TCDn_SADDR Address 4000_8000h base 1000h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SADDR W R...

Страница 463: ...ement a circular data queue easily For data queues requiring power of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the q...

Страница 464: ...3 2 1 0 R NBYTES W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_NBYTES_MLNO field descriptions Field Description 31 0 NBYTES Minor Byte Tr...

Страница 465: ...0h base 1008h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE NBYTES W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Страница 466: ...ed Minor Loop Offset Minor Loop and Offset Enabled DMA_TCDn_NBYTES_MLOFFYES One of three registers this register TCD_NBYTES_MLNO or TCD_NBYTES_MLOFFNO defines the number of bytes to transfer per reque...

Страница 467: ...transferred This is an indivisible operation and cannot be halted It can however be stalled by using the bandwidth control field or via preemption After the minor count is exhausted the SADDR and DADD...

Страница 468: ...ing to the destination data 22 3 26 TCD Signed Destination Address Offset DMA_TCDn_DOFF Address 4000_8000h base 1014h offset 32d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DOFF...

Страница 469: ...l linking NOTE This bit must be equal to the BITER ELINK bit otherwise a configuration error is reported 0 The channel to channel linking is disabled 1 The channel to channel linking is enabled 14 13...

Страница 470: ...lag enables linking to another channel defined by the LINKCH field The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specifi...

Страница 471: ...x x x x Notes x Undefined at reset DMA_TCDn_DLASTSGA field descriptions Field Description 31 0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descrip...

Страница 472: ...fter the last write of each minor loop This behavior is a side effect of reducing start up latency 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for 4 cycles after each R W 11 eDMA engine...

Страница 473: ...rmat The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution 3 DREQ Disable Request If this flag is set the eDMA hardwa...

Страница 474: ...defined by BITER LINKCH The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specified channel If channel linking disables the...

Страница 475: ...CDn_BITER ELINK bit is cleared the TCDn_BITER register is defined as follows Address 4000_8000h base 101Eh offset 32d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 Read ELINK BITER Write Reset x x x x...

Страница 476: ...ld must be set equal to the corresponding CITER field otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field is reloaded into the CITER field...

Страница 477: ...module then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is complete the activ...

Страница 478: ...n write processing continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic...

Страница 479: ...he transfer control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is reported when the...

Страница 480: ...tion count at the point of the fault When a system bus error occurs the channel terminates after the next transfer Due to pipeline effect the next transfer is already in progress when the bus error is...

Страница 481: ...priority channel After the preempting channel has completed all its minor loop data transfers the preempted channel is restored and resumes execution After the restored channel completes one read wri...

Страница 482: ...ernal peripheral bus reads require two wait states and internal peripheral bus writes three wait states when viewed from the system bus data phase All internal peripheral bus accesses are 32 bits in s...

Страница 483: ...itiated requests start at this point with the registering of the user write to TCDn word 7 3 Channel arbitration begins 4 Channel arbitration completes The transfer control descriptor local memory rea...

Страница 484: ...s DMA requests can be processed every 11 5 cycles 4 4 5 2 3 This is the time from Cycle 4 to Cycle x 5 The resulting peak request rate as a function of the system frequency is shown in the following t...

Страница 485: ...write zero wait states on the system bus from a cold start where no channel is executing and eDMA is idle are 11 cycles for a software that is a TCDn_CSR START bit request 12 cycles for a hardware tha...

Страница 486: ...e arbitration and priority levels written into the programmer s model The eDMA engine reads the entire TCD including the TCD control and status fields as shown in the following table for the selected...

Страница 487: ...nterrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes The following figure shows how each DMA request initiates one minor loop transfer or iterati...

Страница 488: ...per channel basis with the exception of channel priority error ES CPE For all error types other than channel priority error the channel number causing the error is recorded in the Error Status regist...

Страница 489: ...enabled For example the following TCD entry is configured to transfer 16 bytes of data The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration The source memory...

Страница 490: ...8 third iteration of the minor loop g Read byte from location 0x100C read byte from location 0x100D read byte from 0x100E read byte from 0x100F h Write 32 bits to location 0x200C last iteration of the...

Страница 491: ...bits to location 0x2004 second iteration of the minor loop e Read byte from location 0x1008 read byte from location 0x1009 read byte from 0x100A read byte from 0x100B f Write 32 bits to location 0x20...

Страница 492: ...yte from 0x101E read byte from 0x101F h Write 32 bits to location 0x201C last iteration of the minor loop major loop complete 14 eDMA engine writes TCDn_SADDR 0x1000 TCDn_DADDR 0x2000 TCDn_CITER 2 TCD...

Страница 493: ...hen using software initiated service requests The first is to read the TCDn_CITER field and test for a change Another method may be extracted from the sequence shown below The second method is to test...

Страница 494: ...true TCDn_SADDR TCDn_DADDR and TCDn_NBYTES values if read while a channel executes The true values of the SADDR DADDR and NBYTES are the values the eDMA engine currently uses in its internal register...

Страница 495: ...k is made after each iteration of the major loop except for the last When the major loop is exhausted only the major loop channel link fields are used to determine if a channel link should be made For...

Страница 496: ...SR MAJOR_LINKCH Link channel number when linking at end of major loop 22 5 7 Dynamic programming This section provides recommended methods to change the programming model during channel execution 22 5...

Страница 497: ...lear the TCD done bit before writing the TCD major e_link bit The TCD done bit is cleared automatically by the eDMA engine after a channel begins execution 22 5 7 3 Dynamic scatter gather Scatter gath...

Страница 498: ...the TCD major linkch bits may be used for other purposes This method uses the TCD major linkch field as a TCD indentification ID 1 When the descriptors are built write a unique TCD ID in the TCD major...

Страница 499: ...ecuting with a destination address daddr that was calculated using a scatter gather address written in the next step instead of a dlast final offest value 2 Write theTCD dlast_sga field with the scatt...

Страница 500: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 500 Freescale Semiconductor Inc...

Страница 501: ...system External Watchdog Monitor EWM is designed to monitor external circuits as well as the MCU software flow This provides a back up mechanism to the internal watchdog that resets the MCU s CPU and...

Страница 502: ...the EWM s counter freezes There are two possible ways to exit from Stop mode On exit from stop mode through a reset the EWM remains disabled On exit from stop mode by an interrupt the EWM is re enabl...

Страница 503: ...ntry of debug mode it remains disabled 23 1 3 Block Diagram This figure shows the EWM block diagram Clock Gating Cell EWM_out EWM Out Logic EWM_out OR Low Power Clock Enable Counter Overflow CPU Reset...

Страница 504: ...Control Register EWM_CTRL 8 R W 00h 23 3 1 504 4006_1001 Service Register EWM_SERV 8 W always reads 0 00h 23 3 2 505 4006_1002 Compare Low Register EWM_CMPL 8 R W 00h 23 3 3 505 4006_1003 Compare Hig...

Страница 505: ...WM_SERV The SERV register provides the interface from the CPU to the EWM module It is write only and reads of this register return zero Address 4006_1000h base 1h offset 4006_1001h Bit 7 6 5 4 3 2 1 0...

Страница 506: ...clocks time for the CPU to service the EWM counter NOTE This register can be written only once after a CPU reset Writing this register more than once generates a bus transfer error NOTE The valid valu...

Страница 507: ...the EWM counter can be prescaled as below Prescaled clock frequency low power clock source frequency 1 CLK_DIV 23 4 Functional Description The following sections describe functional details of the EW...

Страница 508: ...ister When the EWM_out pin is asserted it can only be deasserted by forcing a MCU reset Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset 23 4 2 Th...

Страница 509: ...reset occurs The EWM compare registers are used to create a service window which is used by the CPU to service refresh the EWM module If the CPU services the EWM when the counter value lies between CM...

Страница 510: ...assert the EWM_out pin irrespective of the EWM_in pin The EWM_out pin is expected to gate critical safety circuits Any illegal service on EWM has no effect on EWM_out 23 4 6 EWM Interrupt When EWM_out...

Страница 511: ...n The watchdog monitors the operation of the system by expecting periodic communication from the software generally known as servicing or refreshing the watchdog If this periodic refreshing does not o...

Страница 512: ...hat WDOG timer is operational NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value Windowed refresh option Provides robust chec...

Страница 513: ...ection WDOG CLK R System reset and SRS register Interrupt IRQ_RST_ EN 1 Invalid Unlock Seq 32 bit Timer Timer Time out Refresh Outside Window Invalid Refresh Seq No config after unlocking No unlock af...

Страница 514: ...clock You can also switch over to an alternate clock source if required through a control register bit 24 3 1 Unlocking and updating the watchdog As long as ALLOW_UPDATE in the watchdog control regis...

Страница 515: ...ed to update them only within a period of 256 bus clock cycles after unlocking This period is known as the watchdog configuration time WCT In addition these register bits can be modified only once aft...

Страница 516: ...operation In this mode of operation a restriction is placed on the point in time within the time out period at which the watchdog can be refreshed The refresh is considered valid only when the watchdo...

Страница 517: ...ock is on a reset occurs or interrupt then reset if enabled The entry into Debug mode within WCT after reset is treated differently The WDOG timer is kept reset to zero and there is no need to unlock...

Страница 518: ...a watchdog test unlock and configure the watchdog The refresh and unlock operations and interrupt are not automatically disabled in the test mode 24 4 1 Quick test In this test the time out value of...

Страница 519: ...pares with the Nth byte of the time out value register In this way the byte N is also tested along with the link between it and the preceding stage No other stages N 2 N 3 and N 1 N 2 are enabled for...

Страница 520: ...of two values of the refresh sequence The watchdog can also generate an interrupt If IRQ_RST_EN is set then on the above mentioned events WDOG_ST_CTRL_L INT_FLG is set generating an interrupt A watchd...

Страница 521: ...ount register WDOG_RSTCNT 16 R W 0000h 24 7 11 527 4005_2016 Watchdog Prescaler register WDOG_PRESC 16 R W 0400h 24 7 12 527 24 7 1 Watchdog Status and Control Register High WDOG_STCTRLH Address 4005_...

Страница 522: ...ables or disables WDOG in Wait mode 0 WDOG is disabled in CPU Wait mode 1 WDOG is enabled in CPU Wait mode 6 STOPEN Enables or disables WDOG in Stop mode 0 WDOG is disabled in CPU Stop mode 1 WDOG is...

Страница 523: ...ns Field Description 15 INTFLG Interrupt flag It is set when an exception occurs IRQRSTEN 1 is a precondition to set this flag INTFLG 1 results in an interrupt being issued followed by a reset WCT lat...

Страница 524: ...ister High WDOG_WINH NOTE You must set the Window Register value lower than the Time out Value Register Address 4005_2000h base 8h offset 4005_2008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WINH...

Страница 525: ...system 24 7 7 Watchdog Refresh register WDOG_REFRESH Address 4005_2000h base Ch offset 4005_200Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGREFRESH Write Reset 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0...

Страница 526: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_TMROUTH field descriptions Field Description 15 0 TIMEROUTHIGH Shows the value of the upper 16...

Страница 527: ...0 0 0 0 0 0 WDOG_PRESC field descriptions Field Description 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 PRESCVAL 3 bit prescaler for the wat...

Страница 528: ...or the lower byte of the refresh or unlock register Take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the refresh register as an example Table 24 14 Refresh for 8 bit acc...

Страница 529: ...or watchdog functional test A maximum time period of 2 clock A cycles plus 2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch where clock A and B...

Страница 530: ...nal test mode and therefore you should pull the watchdog out of the functional test mode within WCT time of reset After emerging from a reset due to a watchdog functional test you still need to go thr...

Страница 531: ...clock internal or external as a source for the MCU system clock The MCG operates in conjuction with a crystal oscillator which allows an external crystal ceramic resonator or another external clock so...

Страница 532: ...or the fast clock can be selected as the clock source for the MCU Can be used as a clock source for other on chip peripherals Control signals for the MCG external reference low power oscillator clock...

Страница 533: ...or other on chip peripherals MCG FLL Clock MCGFLLCLK is provided as a clock source for other on chip peripherals MCG Fixed Frequency Clock MCGFFCLK is provided as a clock source for other on chip peri...

Страница 534: ...PLLCLKEN IREFS MCG Crystal Oscillator Enable Detect n 0 7 2n Oscillator OSC0 Oscillator OSC2 OSCSEL OSCINIT EREFS HGO RANGE PLLS Phase Detector Charge Pump Internal Filter VCO VCOOUT PLL VDIV 24 25 2...

Страница 535: ...5 3 1 536 4006_4001 MCG Control 2 Register MCG_C2 8 R W 80h 25 3 2 537 4006_4002 MCG Control 3 Register MCG_C3 8 R W Undefined 25 3 3 538 4006_4003 MCG Control 4 Register MCG_C4 8 R W Undefined 25 3 4...

Страница 536: ...ll other RANGE values Divide Factor is 64 010 If RANGE 0 or OSCSEL 1 Divide Factor is 4 for all other RANGE values Divide Factor is 128 011 If RANGE 0 or OSCSEL 1 Divide Factor is 8 for all other RANG...

Страница 537: ...y the smallest amount possible If an FCFTRIM value stored in nonvolatile memory is to be used it is your responsibility to copy that value from the nonvolatile memory location to this bit 5 4 RANGE Fr...

Страница 538: ...TRIM Write Reset x x x x x x x x Notes x Undefined at reset MCG_C3 field descriptions Field Description 7 0 SCTRIM Slow Internal Reference Clock Trim Setting SCTRIM 1 controls the slow internal refere...

Страница 539: ...r DCO Range 00 0 31 25 39 0625 kHz 640 20 25 MHz 1 32 768 kHz 732 24 MHz 01 0 31 25 39 0625 kHz 1280 40 50 MHz 1 32 768 kHz 1464 48 MHz 10 0 31 25 39 0625 kHz 1920 60 75 MHz 1 32 768 kHz 2197 72 MHz 1...

Страница 540: ...y location to this bit 1 A value for FCTRIM is loaded during reset from a factory programmed location 2 A value for SCFTRIM is loaded during reset from a factory programmed location 25 3 5 MCG Control...

Страница 541: ...K0 is zero Table 25 7 PLL External Reference Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10...

Страница 542: ...r BLPE Whenever the CME0 bit is set to a logic 1 the value of the RANGE0 bits in the C2 register should not be changed CME0 bit should be set to a logic 0 before the MCG enters any Stop mode Otherwise...

Страница 543: ...5 register or the VDIV0 4 0 bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock Loss of PLL reference clock will also cause the LOCK0 bit to...

Страница 544: ...t due to internal synchronization between clock domains The IRCST bit will only be updated if the internal reference clock is enabled either by the MCG being in a mode that uses the IRC or by setting...

Страница 545: ...to the new clock mode switch Otherwise FLL filter and frequency values will change 0 FLL filter and FLL frequency will reset on changes to currect clock mode 1 Fll filter and FLL frequency retain thei...

Страница 546: ...re Value Low Register MCG_ATCVL Address 4006_4000h base Bh offset 4006_400Bh Bit 7 6 5 4 3 2 1 0 Read ATCVL Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVL field descriptions Field Description 7 0 ATCVL ATM Com...

Страница 547: ...a interrupt or a reset request is made following a loss of RTC external reference clock The LOCRE1 only has an affect when CME1 is set 0 Interrupt request is generated on a loss of RTC external refer...

Страница 548: ...ed for RTC clock 1 External clock monitor is enabled for RTC clock 4 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 LOCS1 RTC Loss of Clock Status This...

Страница 549: ...ock mode and the C1 CLKS and S CLKST will automatically be set to 2 b10 If entering Normal Stop mode when the MCG is in PEE mode with PLLSTEN 0 the MCG will reset to PBE clock mode and C1 CLKS and S C...

Страница 550: ...to the FLL factor as selected by C4 DRST_DRS and C4 DMX32 bits times the external reference frequency as specified by C1 FRDIV and C2 RANGE See the C4 DMX32 bit description for more details In FEE mo...

Страница 551: ...In PEE mode the MCGOUTCLK is derived from the output of PLL which is controlled by a external reference clock The PLL clock frequency locks to a multiplication factor as specified by its correspondin...

Страница 552: ...signals are static except in the following case MCGPLLCLK is active in Normal Stop mode when PLLSTEN 1 MCGIRCLK is active in Normal Stop mode when all the following conditions become true C1 IRCLKEN...

Страница 553: ...or PLL to be disabled and thus conserve power when these systems are not being used C4 DRST_DRS can not be written while C2 LP is 1 However in some applications it may be desirable to enable the FLL...

Страница 554: ...is enabled along with the enabled external clock monitor For the case when C6 CME0 1 a loss of clock is detected if the OSC0 external reference falls below a minimum frequency floc_high or floc_low de...

Страница 555: ...ing ATC ATME bit to 1 The ATM machine will start auto trimming the selected IRC clock During the autotrim process ATC ATME will remain asserted and will deassert after ATM is completed or an abort occ...

Страница 556: ...calculated expected count value must be multiplied by 128 before storing it in the ATCV register Therefore the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following f...

Страница 557: ...the FLL reference clock in the range of 31 25 kHz to 39 0625 kHz Although the FLL is bypassed it is still on in FBE mode The internal reference can optionally be kept running by setting C1 IRCLKEN Thi...

Страница 558: ...of 1464 will be 48 MHz When using a 32 768 kHz external reference if the maximum mid high range DCO frequency that can be achieved with a 32 768 kHz reference is desired set C4 DRST_DRS bits to 2 b10...

Страница 559: ...er FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part 25 5 3 MCG mode switching When switching between operational modes of the...

Страница 560: ...the reference divider selected by the C1 FRDIV bits PLL_R is the reference divider selected by C5 PRDIV0 bits F is the FLL factor selected by C4 DRST_DRS and C4 DMX32 bits and M is the multiplier sel...

Страница 561: ...ate correct PLL reference frequency a C5 0x01 C5 PRDIV set to 5 b00001 or divide by 2 resulting in a pll reference frequency of 4MHz 2 2 MHz 3 Then FBE must transition either directly to PBE mode or f...

Страница 562: ...ck 4 Lastly PBE mode transitions into PEE mode a C1 0x10 C1 CLKS set to 2 b00 to select the output of the PLL as the system clock source b Loop until S CLKST are 2 b11 indicating that the PLL output i...

Страница 563: ...MODE C2 0x1E C2 LP 1 CHECK CHECK C1 0x10 CHECK CONTINUE IN PEE MODE S PLLST 1 S LOCK 1 S CLKST 10 S CLKST 11 S LP 1 S IREFST 0 S OSCINIT 1 C5 0x01 C5 VDIV 1 Figure 25 15 Flowchart of FEI to PEE mode t...

Страница 564: ...esired first set C2 LP to 1 b BLPE FBE C6 0x00 C6 PLLS clear to 0 to select the FLL At this time with C1 FRDIV value of 3 b010 the FLL divider is set to 128 resulting in a reference frequency of 4 MHz...

Страница 565: ...d as the reference clock source c Loop until S CLKST are 2 b01 indicating that the internal reference clock is selected to feed MCGOUTCLK 4 Lastly FBI transitions into BLPI mode a C2 0x02 C2 LP is 1 C...

Страница 566: ...IREFST 0 CHECK S CLKST 01 YES NO YES C2 LP 1 C6 0x00 IN BLPE MODE IN BLPE MODE NO YES C2 0x1C C2 LP 0 C2 0x1E ENTER BLPE MODE C2 LP 1 Figure 25 16 Flowchart of PEE to BLPI mode transition using an 4...

Страница 567: ...to 2 b00 to select the output of the FLL as system clock source C1 FRDIV remain at 3 b010 or divide by 128 for a reference of 4 MHz 128 31 25 kHz C1 IREFS cleared to 0 selecting the external referenc...

Страница 568: ...ill switch back to 640 C1 0x10 C2 0x00 C2 0x1C CHECK CHECK CHECK S OSCINIT 1 CONTINUE IN FEE MODE NO NO NO YES YES YES START IN BLPI MODE S IREFST 0 S CLKST 00 Figure 25 17 Flowchart of BLPI to FEE mo...

Страница 569: ...MHz 8 32 MHz crystals and resonators High Range mode Automatic Gain Control AGC to optimize power consumption in high frequency ranges 3 8 MHz 8 32 MHz using low power mode High gain option in freque...

Страница 570: ...ils for the external reference clock source in this MCU The figure found here shows the block diagram of the OSC module XTAL EXTAL XTL_CLK Mux 4096 Counter OSC Clock Enable STOP O SCERCLK_UNDIV ERCLKE...

Страница 571: ...l possible connections Table 26 2 External Caystal Resonator Connections Oscillator Mode Connections Low frequency 32 kHz low power Connection 1 Low frequency 32 kHz high gain Connection 2 Connection...

Страница 572: ...xP bits OSC VSS Cx Cy RF Crystal or Resonator XTAL EXTAL Figure 26 4 Crystal Ceramic Resonator Connections Connection 3 26 6 External Clock Connections In external clock mode the pins can be connected...

Страница 573: ...n page 4006_5000 OSC Control Register OSC_CR 8 R W 00h 26 71 1 573 4006_5002 OSC_DIV OSC_OSC_DIV 8 R W 00h 26 71 2 575 26 71 1 OSC Control Register OSC_CR NOTE After OSC is enabled and starts generati...

Страница 574: ...served This field is reserved This read only field is reserved and always has the value 0 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load 0 Disable the selection 1 Add 2...

Страница 575: ...This read only field is reserved and always has the value 0 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 Reserved This field is reserved This read on...

Страница 576: ...its 26 8 1 1 Off The OSC enters the Off state when the system does not require OSC clocks Upon entering this state XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by...

Страница 577: ..._CLK_OUT Its frequency is determined by the external components being used 26 8 1 4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selection bi...

Страница 578: ...al capacitors could be used 26 8 2 2 Low Frequency Low Power Mode In low frequency low power mode the oscillator uses a gain control loop to minimize power consumption As the oscillation amplitude inc...

Страница 579: ...provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels 26 8 3 Counter The oscillator output clock OSC_CLK_OUT is gated off until the...

Страница 580: ...gister settings If CR ERCLKEN and CR EREFSTEN are set before entry to Low Leakage Stop modes the OSC is still functional in these modes After waking up from Very Low Leakage Stop VLLSx modes all OSC r...

Страница 581: ...C 27 1 1 Features and Modes The key features of the RTC oscillator are as follows Supports 32 kHz crystals with very low power Consists of internal feed back resistor Consists of internal programmable...

Страница 582: ...n to find out which signals are actually connected to the external pins Table 27 1 RTC Signal Descriptions Signal Description I O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O 27 2 1 EXTAL32 O...

Страница 583: ...supplies the negative resistor for the RTC oscillator The gain of the amplifier is controlled by the amplitude detector which optimizes the power consumption A schmitt trigger is used to translate the...

Страница 584: ...There is no reset state associated with the RTC oscillator 27 7 Interrupts The RTC oscillator does not generate any interrupts Reset Overview K22F Sub Family Reference Manual Rev 3 7 2014 584 Freescal...

Страница 585: ...ation of the memory and uses this information to ensure a proper interface The following table shows the supported read write operations Flash memory type Read Write Program flash memory 8 bit 16 bit...

Страница 586: ...t 64 bit line size cache for a total of thirty two 64 bit entries with controls for replacement algorithm and lock per way for each bank Single entry buffer per bank Invalidation control for the specu...

Страница 587: ...visible writes must occur after a programming or erase event is completed and before the new memory image is accessed The cache is a 4 way set associative cache with 8 sets The ways are numbered 0 3...

Страница 588: ...4001_F13C Cache Tag Storage FMC_TAGVDW1S7 32 R W 0000_0000h 28 4 5 601 4001_F140 Cache Tag Storage FMC_TAGVDW2S0 32 R W 0000_0000h 28 4 6 602 4001_F144 Cache Tag Storage FMC_TAGVDW2S1 32 R W 0000_0000...

Страница 589: ...32 R W 0000_0000h 28 4 9 604 4001_F240 Cache Data Storage upper word FMC_DATAW1S0U 32 R W 0000_0000h 28 4 10 604 4001_F244 Cache Data Storage lower word FMC_DATAW1S0L 32 R W 0000_0000h 28 4 11 605 40...

Страница 590: ...F2A0 Cache Data Storage upper word FMC_DATAW2S4U 32 R W 0000_0000h 28 4 12 605 4001_F2A4 Cache Data Storage lower word FMC_DATAW2S4L 32 R W 0000_0000h 28 4 13 606 4001_F2A8 Cache Data Storage upper wo...

Страница 591: ...torage lower word FMC_DATAW3S5L 32 R W 0000_0000h 28 4 15 607 4001_F2F0 Cache Data Storage upper word FMC_DATAW3S6U 32 R W 0000_0000h 28 4 14 606 4001_F2F4 Cache Data Storage lower word FMC_DATAW3S6L...

Страница 592: ...led based on the logical number of the requesting crossbar switch master This field is further qualified by the PFBnCR BxDPE BxIPE bits 0 Prefetching for this master is enabled 1 Prefetching for this...

Страница 593: ...oth read and write accesses may be performed by this master 11 10 M5AP 1 0 Master 5 Access Protection This field controls whether read and write access to the flash are allowed based on the logical ma...

Страница 594: ...nd write access to the flash are allowed based on the logical master number of the requesting crossbar switch master 00 No access may be performed by this master 01 Only read accesses may be performed...

Страница 595: ...s time of the flash array expressed in system clock cycles and RWSC is defined as Access time of flash array system clocks RWSC 1 The FMC automatically calculates this value based on the ratio of the...

Страница 596: ...buffer and single entry buffer are immediately cleared This bit always reads as zero 0 Speculation buffer and single entry buffer are not affected 1 Invalidate clear speculation buffer and single ent...

Страница 597: ...s or speculative accesses are initiated in response to instruction fetches 0 Do not prefetch in response to instruction fetches 1 Enable prefetches in response to instruction fetches 0 B0SEBE Bank 0 S...

Страница 598: ...s read only field defines the number of wait states required to access the bank 1 flash memory The relationship between the read access time of the flash array expressed in system clock cycles and RWS...

Страница 599: ...ata Prefetch Enable This bit controls whether prefetches or speculative accesses are initiated in response to data references 0 Do not prefetch in response to data references 1 Enable prefetches in re...

Страница 600: ...R 0 tag 18 5 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag 18 5 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW0Sn field descriptions Field Descrip...

Страница 601: ...0 tag 18 5 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag 18 5 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW1Sn field descriptions Field Descript...

Страница 602: ...R 0 tag 18 5 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag 18 5 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW2Sn field descriptions Field Descrip...

Страница 603: ...8 5 14 bit tag for cache entry 4 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 valid 1 bit valid for cache entry 28 4 8 Cache Data Storage upper word...

Страница 604: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW0SnL field descriptions Field Description 31 0 data 31 0 Bits 31 0 of data entry 28 4 10 Cache Data Storage upper word FMC_DATAW1SnU The cache of 64...

Страница 605: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnL field descriptions Field Description 31 0 data 31 0 Bits 31 0 of data entry 28 4 12 Cache Data Storage upper word FMC_DATAW2SnU The cache of 64...

Страница 606: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnL field descriptions Field Description 31 0 data 31 0 Bits 31 0 of data entry 28 4 14 Cache Data Storage upper word FMC_DATAW3SnU The cache of 64...

Страница 607: ...0 0 0 0 0 0 0 0 0 FMC_DATAW3SnL field descriptions Field Description 31 0 data 31 0 Bits 31 0 of data entry 28 5 Functional description The FMC is a flash acceleration unit with flexible buffers for u...

Страница 608: ...egister controls enable buffering and prefetching per memory bank and access type instruction fetch or data reference The cache also supports 3 types of LRU replacement algorithms LRU per set across a...

Страница 609: ...stalls waiting for flash memory data to be returned None of the data is already stored in the cache or speculation buffer In this scenario the sequence of events for accessing the four longwords is as...

Страница 610: ...plication is executing flash memory commands the FMC s cache might need to be disabled and or flushed to prevent the possibility of returning stale data Use the PFB0CR CINV_WAY field to invalidate the...

Страница 611: ...bits from the 1 state erased to the 0 state programmed Only the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in the eras...

Страница 612: ...horized access to selected code segments Automated built in program and erase algorithms with verify 29 1 1 2 Other Flash Memory Module Features Internal high voltage supply generator for flash memory...

Страница 613: ...sh block A macro within the flash memory module which provides the nonvolatile memory storage Flash Memory Module All flash blocks plus a flash management unit providing high level control and an inte...

Страница 614: ...pon readout Since erased 1 states are subject to degradation just like programmed 0 states the data retention limit may be reached from the last erase operation not from the programming time RWW Read...

Страница 615: ...ion Register FOPT 0x0_040C 1 Flash security byte Refer to the description of the Flash Security Register FSEC 29 3 2 Program Flash IFR Map The program flash IFR is nonvolatile information memory that...

Страница 616: ...o the user The Program Once Field can be read any number of times This section of the program flash IFR is accessed in 4 byte or 8 Byte records using the Read Once and Program Once commands see Read O...

Страница 617: ...ct Registers FTFA_FCCOB5 8 R W 00h 29 33 5 623 4002_000B Flash Common Command Object Registers FTFA_FCCOB4 8 R W 00h 29 33 5 623 4002_000C Flash Common Command Object Registers FTFA_FCCOBB 8 R W 00h 2...

Страница 618: ...r only Access Registers FTFA_SACCH0 8 R Undefined 29 33 8 627 4002_0024 Supervisor only Access Registers FTFA_SACCL3 8 R Undefined 29 33 8 627 4002_0025 Supervisor only Access Registers FTFA_SACCL2 8...

Страница 619: ...teed The RDCOLERR bit is cleared by writing a 1 to it Writing a 0 to RDCOLERR has no effect 0 No collision error detected 1 Collision error detected 5 ACCERR Flash Access Error Flag Indicates an illeg...

Страница 620: ...CCIE Command Complete Interrupt Enable Controls interrupt generation when a flash command completes 0 Command complete interrupt disabled 1 Command complete interrupt enabled An interrupt request is...

Страница 621: ...field is reserved and always has the value 0 0 Reserved This field is reserved This read only field is reserved and always has the value 0 29 33 3 Flash Security Register FTFA_FSEC This read only reg...

Страница 622: ...has visibility of the current flash contents The state of the FSLACC bits is only relevant when SEC is set to secure When SEC is set to unsecure the FSLACC setting does not matter 00 Freescale factor...

Страница 623: ...l bytes within the set append a 0 B hex identifier to the FCCOB register name FCCOB0 FCCOB1 FCCOBB Address 4002_0000h base 4h offset 1d i where i 0d to 11d Bit 7 6 5 4 3 2 1 0 Read CCOBn Write Reset 0...

Страница 624: ...ata Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness The FCCOB register group uses a big endian addressing convention For all command paramet...

Страница 625: ...nfiguration Field Then reprogram the program flash protection byte Address 4002_0000h base 10h offset 1d i where i 0d to 3d Bit 7 6 5 4 3 2 1 0 Read PROT Write Reset x x x x x x x x Notes x Undefined...

Страница 626: ...flash region is protected 1 Program flash region is not protected 29 33 7 Execute only Access Registers FTFA_XACCn The XACC registers define which program flash segments are restricted to data read o...

Страница 627: ...nt is accessible as data or in execute mode 29 33 8 Supervisor only Access Registers FTFA_SACCn The SACC registers define which program flash segments are restricted to supervisor only or user and sup...

Страница 628: ...ons Field Description 7 0 SA Supervisor only access control 0 Associated segment is accessible in supervisor mode only 1 Associated segment is accessible in user or supervisor mode 29 33 9 Flash Acces...

Страница 629: ...number of program flash segments that are available for XACC and SACC permissions All bits in the register are read only The contents of this register are loaded during the reset sequence Address 4002...

Страница 630: ...2n program flash sizes four registers typically protect 32 regions of the program flash memory as shown in the following figure Program flash size 32 Program flash size 32 Program flash size 32 Progr...

Страница 631: ...0 0x0_0000 Program flash Last program flash address Program flash size 64 XACCL3 XA1 Program flash size 64 XACCL3 XA2 Program flash size 64 XACCL3 XA3 Program flash size 64 XACCL3 XA4 Program flash si...

Страница 632: ...odule can generate interrupt requests to the MCU upon the occurrence of various flash events These interrupt events and their associated status and control bits are shown in the following table Table...

Страница 633: ...lash command is running CCIF 0 NOTE While the MCU is in very low power modes VLPR VLPW VLPS the flash memory module does not accept flash commands 29 4 5 Functional Modes of Operation The flash memory...

Страница 634: ...eral bus writes The user cannot initiate any further flash commands until notified that the current command has completed The flash command structure and operation are detailed in Flash Command Operat...

Страница 635: ...s a blocking mechanism that prevents a new command from launching can t clear FSTAT CCIF if the previous command resulted in an access error FSTAT ACCERR 1 or a protection violation FSTAT FPVIOL 1 In...

Страница 636: ...ted back to the user via the FCCOB and FSTAT registers 4 The flash memory module sets FSTAT CCIF signifying that the command has completed The flow for a generic command write sequence is illustrated...

Страница 637: ...k is erased then release MCU security 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flash 0 IFR 0x43 Program Once IFR One time program of 4 bytes of a dedicated 64 byte f...

Страница 638: ...nded flash array reads to the MCU always use the standard un margined read reference level Only the normal read level should be employed during normal flash usage The non standard user and factory mar...

Страница 639: ...l factory programming 29 4 11 Flash Command Description This section describes all flash commands that can be launched by a command write sequence The flash memory module sets the FSTAT ACCERR bit and...

Страница 640: ...reads all locations within the specified section of flash memory If the flash memory module fails to read all 1s that is the flash section is not erased FSTAT MGSTAT0 is set FSTAT CCIF sets after the...

Страница 641: ...comparison at margin 1 fails FSTAT MGSTAT0 is set The flash memory module then sets the read margin for 0s re reads and compares again If the comparison at margin 0 fails FSTAT MGSTAT0 is set FSTAT CC...

Страница 642: ...emory module The special purpose memory resources available include program flash IFR space and the Version ID field Each resource is assigned a select code as shown in Table 29 53 Table 29 52 Read Re...

Страница 643: ...T ACCERR 29 4 11 4 Program Longword Command The Program Longword command programs four previously erased bytes in the program flash memory using an embedded algorithm CAUTION A flash memory location m...

Страница 644: ...able 29 56 Program Longword Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR An invalid flash address is supplied FSTAT ACCERR Flash address...

Страница 645: ...on command to verify all bits are erased 29 4 11 5 1 Suspending an Erase Flash Sector Operation To suspend an Erase Flash Sector operation set the FCNFG ERSSUSP bit see Flash Configuration Field Descr...

Страница 646: ...plete If the minimum period is continually violated i e the suspend requests come repeatedly and too quickly no forward progress is made by the Erase Flash Sector algorithm The resume suspend sequence...

Страница 647: ...xecute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Complete...

Страница 648: ...ased by setting the FSEC SEC field to the unsecure state The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blocks comma...

Страница 649: ...value 8 Program Once byte 4 value index 0x10 0x13 9 Program Once byte 5 value index 0x10 0x13 10 Program Once byte 6 value index 0x10 0x13 11 Program Once byte 7 value index 0x10 0x13 After clearing...

Страница 650: ...ogram Once byte 6 value index 0x10 0x13 11 Program Once byte 7 value index 0x10 0x13 After clearing CCIF to launch the Program Once command the flash memory module first verifies that the selected rec...

Страница 651: ...field see Flash Configuration Field Description are erased by the Erase All Blocks command If the erase verify fails the FSTAT MGSTAT0 bit is set The CCIF flag is set after the Erase All Blocks operat...

Страница 652: ...FCNFG ERSAREQ bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command 29 4 11 10 Verify Backdoor Access Key Command The V...

Страница 653: ...door Access Key command fails with an access error The CCIF flag is set after the Verify Backdoor Access Key operation completes Table 29 69 Verify Backdoor Access Key Command Error Handling Error Con...

Страница 654: ...the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field This assumes that you are starting from a mode where the...

Страница 655: ...kdoor Access Key command A reset of the chip is the only method to re enable the Verify Backdoor Access Key command when a comparison fails After the backdoor keys have been correctly matched the chip...

Страница 656: ...rked by setting CCIF which enables flash user commands If a reset occurs while any flash command is in progress that command is immediately aborted The state of the word being programmed or the sector...

Страница 657: ...e that enables In System Programming ISP of flash memory contents in a 32 bit general purpose microcontroller Memory contents can be read erased programmed from an external source in a format that is...

Страница 658: ...ollowing features Serial interface that is compatible with a subset of the SPI format Ability to read erase and program flash memory Ability to reset the microcontroller allowing it to boot from the f...

Страница 659: ...ntents of the flash memory The serial data out from the EzPort is tri stated unless data is being driven This allows the signal to be shared among several different EzPort or compatible devices in par...

Страница 660: ...D is the serial data in for data transfers EZP_D is registered on the rising edge of EZP_CK All commands addresses and data are shifted in most significant bit first When the EzPort is driving output...

Страница 661: ...mber of data bytes programmed must be a multiple of 4 5 Bulk Erase is accepted when security is set and only when the BEDIS status field is not set 6 The flash will be in NVM Special mode restricting...

Страница 662: ...0 EZP_CK EZP_CS EZP_D EZP_Q Figure 30 4 Read Status Register command sequence The Read Status Register RDSR command returns the contents of the EzPort status register Table 30 3 EzPort status register...

Страница 663: ...sociated with the command 0 Disables the following write command 1 Enables the following write command 2 BEDIS Bulk erase disable Indicates whether bulk erase BE is disabled when flash is secure 0 BE...

Страница 664: ...flash memory regions returns unknown data See Flash memory map for EzPort access For this command to return the correct data the EzPort clock EZP_CK must run at the internal system clock divided by ei...

Страница 665: ...ter the command word and must be a 32 bit aligned address with the two LSBs being zero As data is shifted in the EzPort buffers the data in System RAM before sequentially moving the data into flash us...

Страница 666: ...not accepted if the WEF WIP or FS field is set or if the WEN field is not set in the EzPort status register 30 3 1 8 Bulk Erase CMD 7 0 0xC7 EZP_CK EZP_CS EZP_D EZP_Q Figure 30 9 Bulk Erase command se...

Страница 667: ...s not accepted if the WIP field is set in the EzPort status register 30 3 1 10 Write FCCOB Registers CMD 7 0 0xBA FCCOB_0 7 0 FCCOB_1 7 0 FCCOB_B 7 0 EZP_CK EZP_CS EZP_D EZP_Q Figure 30 11 Write FCCOB...

Страница 668: ...s of the flash common command object registers After receiving the command EzPort waits for one dummy byte of data before returning FCCOB register data starting at FCCOB 0 and ending with FCCOB B This...

Страница 669: ...Access Valid start address Size Flash block Valid commands 0x0000_0000 See device s chip configuration details Flash READ FAST_READ SP SE BE Chapter 30 EzPort K22F Sub Family Reference Manual Rev 3 7...

Страница 670: ...Flash memory map for EzPort access K22F Sub Family Reference Manual Rev 3 7 2014 670 Freescale Semiconductor Inc...

Страница 671: ...RC module include Hardware CRC generator circuit using a 16 bit or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose input data or output data the C...

Страница 672: ...ny CRC calculation in progress stops when the MCU enters a low power mode that disables the module clock It resumes after the clock is enabled or via the system reset for exiting the low power mode Cl...

Страница 673: ...1 0 R HU HL LU LL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_DATA field descriptions Field Description 31 24 HU CRC High Upper Byte In 16 bit CRC mode CTRL TCRC is 0...

Страница 674: ...l Half word Writable and readable in 32 bit CRC mode CTRL TCRC is 1 This field is not writable in 16 bit CRC mode CTRL TCRC is 0 15 0 LOW Low Polynominal Half word Writable and readable in both 32 bit...

Страница 675: ...ransposed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FXOR Complement Read Of CRC Data Register Some CRC protocols require the final checksum to b...

Страница 676: ...To compute a 16 bit CRC 1 Clear CRC_CTRL TCRC to enable 16 bit CRC mode 2 Program the transpose and complement options in the CTRL register as required for the CRC calculation See Transpose feature an...

Страница 677: ...RC result complement for details 31 3 3 Transpose feature By default the transpose feature is not enabled However some CRC standards require the input data and or the final checksum to be transposed T...

Страница 678: ...5 Transpose type 01 3 CTRL TOT or CTRL TOTR is 10 Both bits in bytes and bytes are transposed reg 31 0 becomes reg 0 7 reg 8 15 reg 16 23 reg 24 31 31 31 0 0 Figure 31 6 Transpose type 10 4 CTRL TOT o...

Страница 679: ...transposition resides in the CRC HU HL fields The user software must account for this situation when reading the 16 bit CRC result so reading 32 bits is preferred 31 3 4 CRC result complement When CTR...

Страница 680: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 680 Freescale Semiconductor Inc...

Страница 681: ...means of generating the required entropy needed to create random data The random words generated by RNGA are loaded into an output register OR RNGA is designed to generate an error interrupt if not m...

Страница 682: ...entropy can be used along with RNGA to generate the seed to the pseudorandom algorithm The more random sources combined to create the seed the better The following is a list of sources that can be eas...

Страница 683: ...8 RNGA Entropy Register RNG_ER 32 W always reads 0 0000_0000h 32 3 3 687 4002_900C RNGA Output Register RNG_OR 32 R 0000_0000h 32 3 4 687 32 3 1 RNGA Control Register RNG_CR Controls the operation of...

Страница 684: ...r interrupt to the interrupt controller when an OR underflow condition occurs An OR underflow condition occurs when you read OR RANDOUT and SR OREG_LVL 0 See the Output Register OR description 0 Not m...

Страница 685: ...23 16 OREG_SIZE Output Register Size Indicates the size of the Output OR register in terms of the number of 32 bit random data words it can hold 1 One word this value is fixed 15 8 OREG_LVL Output Re...

Страница 686: ...condition has occurred since you last read this register SR or RNGA was reset regardless of whether the error interrupt is masked CR INTM An OR underflow condition occurs when you read OR RANDOUT and...

Страница 687: ...its pseudorandom algorithm NOTE Specifying a value for this field is optional but recommended You can write to this field at any time during operation 32 3 4 RNGA Output Register RNG_OR Stores a rand...

Страница 688: ...control signals Figure 32 5 RNGA block diagram 32 4 1 Output OR register The Output OR register provides temporary storage for random data generated by the core engine control logic The Status SR regi...

Страница 689: ...new random data word If SR OREG_LVL 0 then the control block loads the new random data into OR and set SR OREG_LVL 1 else the new data is discarded 32 4 2 2 Core engine The core engine block contains...

Страница 690: ...For application information see Overview Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 690 Freescale Semiconductor Inc...

Страница 691: ...e 33 1 1 Features Following are the features of the ADC module Linear successive approximation algorithm with up to 16 bit resolution Up to four pairs of differential and 24 single ended external anal...

Страница 692: ...t the clock Selectable hardware conversion trigger with hardware channel select Automatic compare with interrupt for less than greater than or equal to within range or out of range programmable value...

Страница 693: ...onversion trigger control Clock divide Control sequencer Bus clock SAR converter Compare logic Offset subtractor Averager Formatting ADLSMP ADLSTS ADLPC ADHSC initialize sample convert transfer abort...

Страница 694: ...cted internally to VSS If externally available connect the VSSA pin to the same voltage potential as VSS 33 2 3 Voltage Reference Select VREFSH and VREFSL are the high and low reference voltages for t...

Страница 695: ...ed as single ended inputs if SC1n DIFF is low In certain MCU configurations some DADMx inputs may also be used as single ended inputs if SC1n DIFF is low See the chip configuration chapter for ADC con...

Страница 696: ...alibration Value Register ADC1_CLMD 32 R W 0000_000Ah 33 3 18 714 4002_7058 ADC Minus Side General Calibration Value Register ADC1_CLMS 32 R W 0000_0020h 33 3 19 714 4002_705C ADC Minus Side General C...

Страница 697: ...4C ADC Plus Side General Calibration Value Register ADC0_CLP0 32 R W 0000_0020h 33 3 17 713 4003_B054 ADC Minus Side General Calibration Value Register ADC0_CLMD 32 R W 0000_000Ah 33 3 18 714 4003_B05...

Страница 698: ...n all 1s Writing any of the SC1n registers while that specific SC1n register is actively controlling a conversion aborts the current conversion None of the SC1B SC1n registers are used for software tr...

Страница 699: ...ions in the bitfield setting descriptions might not be available for your device For the actual ADC channel assignments for your device see the Chip Configuration details The successive approximation...

Страница 700: ...ed 11001 Reserved 11010 When DIFF 0 Temp Sensor single ended is selected as input when DIFF 1 Temp Sensor differential is selected as input 11011 When DIFF 0 Bandgap single ended is selected as input...

Страница 701: ...long sample time select bits ADLSTS 1 0 can select the extent of the long sample time 0 Short sample time 1 Long sample time 3 2 MODE Conversion mode selection Selects the ADC resolution mode 00 When...

Страница 702: ...ock Output Enable Enables the asynchronous clock source and the clock source output regardless of the conversion and status of CFG1 ADICLK Based on MCU configuration the asynchronous clock may be used...

Страница 703: ...ry status and channel control register there is a corresponding data result register Unused bits in R n are cleared in unsigned right aligned modes and carry the sign bit MSB in sign extended 2 s comp...

Страница 704: ...ata result 33 3 5 Compare Value Registers ADCx_CVn The Compare Value Registers CV1 and CV2 contain a compare value used to compare the conversion result when the compare function is enabled that is SC...

Страница 705: ...Address Base address 20h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ADACT ADTRG ACFE ACFGT ACR...

Страница 706: ...de range not inclusive functionality based on the values placed in CV1 and CV2 1 Configures greater than or equal to threshold outside and inside ranges inclusive functionality based on the values pla...

Страница 707: ...8 7 6 5 4 3 2 1 0 R 0 CAL CALF 0 ADCO AVGE AVGS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_SC3 field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reser...

Страница 708: ...only field is reserved and always has the value 0 3 ADCO Continuous Conversion Enable Enables continuous conversions 0 One conversion or one set of conversions if the hardware average function is ena...

Страница 709: ...on 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 0 OFS Offset Error Correction Value 33 3 9 ADC Plus Side Gain Register ADCx_PG The Plus Side Gai...

Страница 710: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ADCx_MG field descriptions Field Description 31 16 Reserved This field is reserved Thi...

Страница 711: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLPS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ADCx_CLPS field descriptions Field Description 31 6 Reserve...

Страница 712: ...n 31 9 Reserved This field is reserved This read only field is reserved and always has the value 0 8 0 CLP3 Calibration Value Calibration Value 33 3 15 ADC Plus Side General Calibration Value Register...

Страница 713: ...field is reserved and always has the value 0 6 0 CLP1 Calibration Value Calibration Value 33 3 17 ADC Plus Side General Calibration Value Register ADCx_CLP0 For more information see CLPD register des...

Страница 714: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 ADCx_CLMD field descriptions Field Description 31 6 Reserved This field is reserved This read only field is reserved and always has the...

Страница 715: ...LM4 Calibration Value Calibration Value 33 3 21 ADC Minus Side General Calibration Value Register ADCx_CLM3 For more information see CLMD register description Address Base address 60h offset Bit 31 30...

Страница 716: ...0 CLM2 Calibration Value Calibration Value 33 3 23 ADC Minus Side General Calibration Value Register ADCx_CLM1 For more information see CLMD register description Address Base address 68h offset Bit 31...

Страница 717: ...output enable is disabled or CFG2 ADACKEN 0 the module is in its lowest power state The ADC can perform an analog to digital conversion on any of the software selectable channels All modes perform con...

Страница 718: ...clock is generated from a clock source within the ADC module When the ADACK clock source is selected it is not required to be active prior to conversion start When it is selected and it is not active...

Страница 719: ...vailable and hardware trigger is enabled that is SC2 ADTRG 1 a conversion is initiated on the rising edge of ADHWT after a hardware trigger select event that is ADHWTSn has occurred If a conversion is...

Страница 720: ...y CFG1 MODE and SC1n DIFF as shown in the description of CFG1 MODE Conversions can be initiated by a software or hardware trigger In addition the ADC module can be configured for Low power operation L...

Страница 721: ...ered operation conversions begin after SC1A is written In hardware triggered operation conversions begin after a hardware trigger If continuous conversions are also enabled a new set of conversions to...

Страница 722: ...Stop mode with ADACK or Alternate Clock Sources not enabled When a conversion is aborted the contents of the data registers Rn are not altered The data registers continue to be the values transferred...

Страница 723: ...onfiguration that is CFG2 ADHSC The frequency of the conversion clock that is fADCK CFG2 ADHSC is used to configure a higher clock input frequency This will allow faster overall conversion times To me...

Страница 724: ...dder SFCAdder 1 x 0x 10 3 ADCK cycles 5 bus clock cycles 1 1 11 3 ADCK cycles 5 bus clock cycles1 1 0 11 5 s 3 ADCK cycles 5 bus clock cycles 0 x 0x 10 5 ADCK cycles 5 bus clock cycles 0 1 11 5 ADCK c...

Страница 725: ...1 2 ADCK cycles Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications 33 4 4 6 Conversion time examples The following examples use the Figure 33 92 and the...

Страница 726: ...uration A configuration for long ADC conversion is 16 bit differential mode with the bus clock selected as the input clock source The input clock divide by 8 ratio selected Bus frequency of 8 MHz Long...

Страница 727: ...s 5 bus clock cycles AverageNum 1 BCT 17 ADCK cycles LSTAdder 0 ADCK cycles HSCAdder 2 The resulting conversion time is generated using the parameters listed in in the preceding table Therefore for bu...

Страница 728: ...e input is sampled and converted the compare values in CV1 and CV2 are used as described in the following table There are six Compare modes as shown in the following table Table 33 112 Compare modes S...

Страница 729: ...hile the MCU is in Wait or Normal Stop modes The ADC interrupt wakes the MCU when the compare condition is met 33 4 6 Calibration function The ADC contains a self calibration function that is required...

Страница 730: ...ear and SC3 CALF to set At the end of a calibration sequence SC1n COCO will be set SC1n AIEN can be used to allow an interrupt to occur at the end of a calibration sequence At the end of the calibrati...

Страница 731: ...de of operation The formatting of the OFS is different from the data result register Rn to preserve the resolution of the calibration value regardless of the conversion mode selected Lower order bits...

Страница 732: ...user defined offset For applications that may change the offset repeatedly during operation store the initial offset calibration value in flash so it can be recovered and added to any user offset adju...

Страница 733: ...s are available as conversion clock sources while in Wait mode The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU See the Chip Configuration...

Страница 734: ...to wake the MCU from Normal Stop mode if the respective ADC interrupt is enabled that is when SC1n AIEN 1 The result register Rn will contain the data from the first completed conversion that occurre...

Страница 735: ...to complete conversions an initialization procedure must be performed A typical sequence is 1 Calibrate the ADC by following the calibration instructions in Calibration function 2 Update CFG to select...

Страница 736: ...ACT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3 ACREN 0 Compare range di...

Страница 737: ...edded control applications requiring an ADC For guidance on selecting optimum external component values and converter parameters see AN4373 Cookbook for SAR ADC Measurements 33 6 1 External pins and r...

Страница 738: ...ference The two pairs are external VREFH and VREFL and alternate VALTH and VALTL These voltage references are selected using SC2 REFSEL The alternate voltage reference pair VALTH and VALTL may select...

Страница 739: ...tween VREFH and VREFL If the input is equal to or exceeds VREFH the converter circuit converts the signal to 0xFFF which is full scale 12 bit representation 0x3FF which is full scale 10 bit representa...

Страница 740: ...it mode 12 in 12 bit mode or 16 in 16 bit mode 33 6 2 3 Noise induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion The ADC accuracy...

Страница 741: ...LSB one time error Reduce the effect of synchronous noise by operating off the asynchronous clock that is ADACK and averaging Noise that is synchronous to ADCK cannot be averaged out 33 6 2 4 Code wi...

Страница 742: ...al non linearity DNL This error is defined as the worst case difference between the actual code width and the ideal code width for all conversions Integral non linearity INL This error is defined as t...

Страница 743: ...is defined as when except for code jitter the converter converts to a lower code for a higher input voltage Missing codes Missing codes are those values never converted for any input value In 8 bit o...

Страница 744: ...Application information K22F Sub Family Reference Manual Rev 3 7 2014 744 Freescale Semiconductor Inc...

Страница 745: ...ull range of the supply voltage The 6 bit DAC is 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed The 64 tap resistor lad...

Страница 746: ...ed for internal functions Two software selectable performance levels Shorter propagation delay at the expense of higher power Low power with longer propagation delay DMA transfer support A comparison...

Страница 747: ...ver the entire supply range 34 1 4 CMP DAC and ANMUX diagram The following figure shows the block diagram for the High Speed Comparator DAC and ANMUX modules Chapter 34 Comparator CMP K22F Sub Family...

Страница 748: ...0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INM Sample input Figure 34 1 CMP DAC and ANMUX block diagram 34 1 5 CMP block diagram...

Страница 749: ...WE 1 the comparator output will be sampled on every bus clock when WINDOW 1 to generate COUTA Sampling does NOT occur when WINDOW 0 The Filter block is bypassed when not in use The Filter block acts a...

Страница 750: ...05 MUX Control Register CMP0_MUXCR 8 R W 00h 34 2 6 755 4007_3008 CMP Control Register 0 CMP1_CR0 8 R W 00h 34 2 1 750 4007_3009 CMP Control Register 1 CMP1_CR1 8 R W 00h 34 2 2 751 4007_300A CMP Filt...

Страница 751: ...his read only field is reserved and always has the value 0 1 0 HYSTCTR Comparator hard block hysteresis control Defines the programmable hysteresis level The hysteresis values associated with each lev...

Страница 752: ...ion delay and lower current consumption 1 High Speed HS Comparison mode selected In this mode CMP has faster output propagation delay and higher current consumption 3 INV Comparator INVERT Allows sele...

Страница 753: ...s field has no effect when CR1 SE 1 In that case the external SAMPLE signal is used to determine the sampling period 34 2 4 CMP Status and Control Register CMPx_SCR Address Base address 3h offset Bit...

Страница 754: ...ing edge on COUT has occurred 1 CFF Analog Comparator Flag Falling Detects a falling edge on COUT when set during normal operation CFF is cleared by writing 1 to it During Stop modes CFF is level sens...

Страница 755: ...it can be programmed to zero only This field is reserved 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 3 PSEL Plus Input Mux Control Determines which...

Страница 756: ...le to assert an interrupt to the processor SCR CFF is set on a falling edge and SCR CFR is set on rising edge of the comparator output The optionally filtered CMPO can be read directly through SCR COU...

Страница 757: ...e s 3A 3B 3B 1 0 0 0x01 0x00 4A 1 0 1 0x01 X Sampled Filtered mode See the Sampled Filtered mode s 4A 4B 4B 1 0 0 0x01 0x00 5A 1 1 0 0x00 X Windowed mode Comparator output is sampled on every rising b...

Страница 758: ...1 Disabled mode 1 In Disabled mode the analog comparator is non functional and consumes no power CMPO is 0 in this mode 34 3 1 2 Continuous mode s 2A 2B IRQ Internal bus INP INM FILTER_CNT INV COUT C...

Страница 759: ...ed mode s 3A 3B IRQ INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 1 WE 0 SE 1 CGMUX COS FILT_PER 1 0 FILT_PER COS 0x01 IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock...

Страница 760: ...s clock Internal bus Polarity select Window control Filter block Interrupt control To other SOC functions Clock prescaler Figure 34 23 Sampled Non Filtered 3B sampling interval internally derived 34 3...

Страница 761: ...MPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt control Clock prescaler To other SOC functions Figure 34 24 Sampled Filtere...

Страница 762: ...that now CR0 FILTER_CNT 1 which activates filter operation 34 3 1 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analog comp...

Страница 763: ...ck COS 0x01 IER F CFR F WINDOW SAMPLE Polarity select Window control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 34 27 Windowed mod...

Страница 764: ...tion Depending upon the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully considered...

Страница 765: ...ched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS FILT_PER 0 1 FILT_PER bus clock COS IER F CFR F WINDOW SAMP...

Страница 766: ...e CMP output pin is latched and does not reflect the compare output state The positive and negative input voltage can be supplied from external pins or the DAC output The MCU can be brought out of the...

Страница 767: ...and the amount of filtering is dependent on user requirements Filtering can become more useful in the absence of an external hysteresis circuit Without external hysteresis high frequency oscillations...

Страница 768: ...NT The values of FPR FILT_PER or SAMPLE period and CR0 FILTER_CNT must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions The probability of...

Страница 769: ...hen SCR IER and SCR CFR are set The interrupt request is asserted SCR IEF and SCR CFF are set The interrupt request is asserted SCR IER and SCR CFR are cleared for a rising edge interrupt The interrup...

Страница 770: ...ils 34 6 CMP Asynchronous DMA support The comparator can remain functional in STOP modes When DMA support is enabled by setting SCR DMAEN and the interrupt is enabled by setting SCR IER SCR IEF or bot...

Страница 771: ...in2 The module can be powered down or disabled when not in use When in Disabled mode DACO is connected to the analog ground VOSEL 5 0 DACO MUX MUX DACEN Vin VRSEL Vin1 Vin2 Figure 34 30 6 bit DAC bloc...

Страница 772: ...orresponding to the chip wide peripheral reset 34 10 DAC clocks This module has a single clock input the bus clock 34 11 DAC interrupts This module has no interrupts DAC resets K22F Sub Family Referen...

Страница 773: ...parator op amps or ADC 35 2 Features The features of the DAC module include On chip programmable reference generator output The voltage output range is from 1 4096 Vin to Vin and the step is 1 4096 Vi...

Страница 774: ...CBFRPBF DACBBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 35 1 DAC block diagram 35 4 Memory map register definition The DAC has registers to control analog comparator...

Страница 775: ...8 R W 00h 35 4 1 776 4003_F011 DAC Data High Register DAC0_DAT8H 8 R W 00h 35 4 2 776 4003_F012 DAC Data Low Register DAC0_DAT9L 8 R W 00h 35 4 1 776 4003_F013 DAC Data High Register DAC0_DAT9H 8 R W...

Страница 776: ...DAC Data High Register DACx_DATnH Address 4003_F000h base 1h offset 2d i where i 0d to 15d Bit 7 6 5 4 3 2 1 0 Read 0 DATA1 Write Reset 0 0 0 0 0 0 0 0 DACx_DATnH field descriptions Field Description...

Страница 777: ...evel 1 The DAC buffer read pointer has reached the watermark level 1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag In FIFO mode it is FIFO nearly empty flag It is set when only one data remains...

Страница 778: ...If DAC software trigger is selected and buffer is enabled writing 1 to this field will advance the buffer read pointer once 0 The DAC soft trigger is not valid 1 The DAC soft trigger is valid 3 LPEN...

Страница 779: ...it DACBUP SR DACBFWMF will be set This allows user configuration of the watermark interrupt In FIFO mode it is FIFO watermark select field 00 In normal mode 1 word In FIFO mode 2 or less than 2 data r...

Страница 780: ...O status is empty It is writable and user can configure it to the same address to reset FIFO as empty 35 5 Functional description The 12 bit DAC module can select one of the two reference inputs DACRE...

Страница 781: ...scribes the different modes of data buffer operation for the DAC module Table 35 79 Modes of DAC data buffer operation Modes Description Buffer Normal mode This is the default mode The buffer works as...

Страница 782: ...Only both byte lanes are written will the write pointer increase User need to make sure 8bit access happened in pair and both upper lower bytes are written There is no requirement on which byte write...

Страница 783: ...the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop In low power stop modes the DAC is fully shut down NOTE The assignment of module modes t...

Страница 784: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 784 Freescale Semiconductor Inc...

Страница 785: ...trimmed in 0 5 mV steps The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC DAC or CMP The v...

Страница 786: ...s ADCs and DACs Refer to the chip configuration details for a description of these options The reference voltage is output on a dedicated output pin when the VREF is enabled The Voltage Reference outp...

Страница 787: ...of operation Having the VREF regulator enabled does increase current consumption In very low power modes it may be desirable to disable the VREF regulator to minimize current consumption Note however...

Страница 788: ...set will be minimized This bit is set during factory trimming of the VREF voltage This bit should be written to 1 to achieve the performance stated in the data sheet If the internal voltage regulator...

Страница 789: ...e is disabled 1 The module is enabled 6 REGEN Regulator enable This bit is used to enable the internal 1 75 V regulator to produce a constant internal voltage supply in order to reduce the sensitivity...

Страница 790: ...rved 36 3 Functional Description The Voltage Reference is a bandgap buffer system Unity gain amplifiers are used The VREF_OUT signal can be used by both internal and external peripherals in low and hi...

Страница 791: ...nd there is no buffered voltage output The Voltage Reference is in standby mode If this mode is first selected and the low power or high power buffer mode is subsequently enabled there will be a delay...

Страница 792: ...n you must wait the longer of Tstup or until SC VREFST 1 when the chop oscillator is not enabled If the chop oscillator is being used you must wait the time specified by Tchop_osc_stup chop oscillator...

Страница 793: ...MODE_LV will not clear SC VREFST but there will be some startup time before the output voltage at the VREF_OUT pin has settled This is the buffer start up delay Tstup and the value is specified in the...

Страница 794: ...Initialization Application Information K22F Sub Family Reference Manual Rev 3 7 2014 794 Freescale Semiconductor Inc...

Страница 795: ...DB can optionally provide pulse outputs Pulse Out s that are used as the sample window in the CMP block 37 1 1 Features Up to 15 trigger input sources and one software trigger source Up to 8 configura...

Страница 796: ...Implementation In this section the following letters refer to the number of output triggers N Total available number of PDB channels n PDB channel number valid from 0 to N 1 M Total available pre tri...

Страница 797: ...ormation 37 1 4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip specific See the chip configuration information for details 37 1 5 Block diagram This d...

Страница 798: ...rrupt TOEx POyDLY2 POyDLY1 Pulse Generation Pulse Out y PDBPOEN y Pulse Out y DAC interval trigger x From trigger mux TOEx DAC external trigger input Control logic PDB counter DAC interval counter x F...

Страница 799: ...he modulus register and the counting is restarted This enables a continuous stream of pre triggers trigger outputs as a result of a single trigger input event Enabled Bypassed The pre trigger and trig...

Страница 800: ...R W 0000_0000h 37 3 8 807 4003_6038 Channel n Control register 1 PDB0_CH1C1 32 R W 0000_0000h 37 3 5 805 4003_603C Channel n Status register PDB0_CH1S 32 R W 0000_0000h 37 3 6 806 4003_6040 Channel n...

Страница 801: ...ir buffers immediately after 1 is written to LDOK 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK...

Страница 802: ...factor selected by MULT 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT 110 Counting uses the peripheral clock divided by 64 times of the mult...

Страница 803: ...DB operation in Continuous mode 0 LDOK Load OK Writing 1 to this bit updates the internal registers of MOD IDLY CHnDLYm DACINTx and POyDLY with the values written to their buffers The MOD IDLY CHnDLYm...

Страница 804: ...eserved This field is reserved This read only field is reserved and always has the value 0 15 0 CNT PDB Counter Contains the current value of the counter 37 3 4 Interrupt Delay register PDBx_IDLY Addr...

Страница 805: ...uration and results registers Application code must only enable the back to back operation of the PDB pre triggers at the leading of the back to back connection chain 0 PDB channel s corresponding pre...

Страница 806: ...for a conversion by one pre trigger from PDB channel n When one conversion which is triggered by one of the pre triggers from PDB channel n is in progress new trigger from PDB channel s corresponding...

Страница 807: ...50h offset 8d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 EXT TOE W Reset 0 0 0 0 0...

Страница 808: ...DAC interval trigger DAC interval trigger triggers DAC 1 0 update when the DAC interval counter is equal to the DACINT Reading these bits returns the value of internal register that is effective for t...

Страница 809: ...y 2 value for the PDB Pulse Out Pulse Out goes low when the PDB counter is equal to the DLY2 Reading this field returns the value of internal register that is effective for the current PDB cycle 37 4...

Страница 810: ...in the following diagram show the pre trigger and trigger outputs of PDB channel n The delays can be independently set using the CHnDLYm registers and the pre triggers can be enabled or disabled in CH...

Страница 811: ...value set in IDLY register the SC PDBIF flag is set A PDB interrupt can be generated if SC PDBIE is set and SC DMAEN is cleared If SC DMAEN is set then the PDB requests a DMA transfer when the SC PDB...

Страница 812: ...ized as shown in the table below Table 37 52 Circumstances of update to the delay registers SC LDMOD Update to the delay registers 00 The internal registers are loaded with the values from their buffe...

Страница 813: ...pt and PDB sequence error interrupt The following table summarizes the interrupts Table 37 53 PDB interrupt summary Interrupt Flags Enable bit PDB Interrupt SC PDBIF SC PDBIE 1 and SC DMAEN 0 PDB Sequ...

Страница 814: ...o 2 then the only values of total peripheral clocks that can be detected are even values if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mo...

Страница 815: ...HCS08 Timer PWM Module TPM used for many years on Freescale s 8 bit microcontrollers The FlexTimer extends the functionality to meet the demands of motor control digital lighting solutions and power c...

Страница 816: ...the same in each FlexTimer All main user access registers are buffered to ease the load on the executing software A number of trigger options exist to determine which registers are updated with this u...

Страница 817: ...eneration of an interrupt when the counter overflows The generation of an interrupt when the fault condition is detected Synchronized loading of write buffered FTM registers Write protection for criti...

Страница 818: ...k diagram The FTM uses one input output I O pin per channel CHn FTM channel n where n is the channel number 0 7 The following figure shows the FTM structure The central component of the FTM is the 16...

Страница 819: ...7V CH6IE CH6F CH1IE CH0IE CH7IE CH7F CH1F CH0F channel 0 interrupt channel 1 interrupt channel 6 interrupt channel 7 interrupt channel 7 match trigger channel 6 output signal channel 6 match trigger c...

Страница 820: ...at each FAULTj input may affect all channels selectively since FAULTM 1 0 and FAULTEN control bits are defined for each pair of channels Because there are several FAULTj inputs maximum of 4 for the FT...

Страница 821: ...003_8028 Channel n Value FTM0_C3V 32 R W 0000_0000h 38 3 7 832 4003_802C Channel n Status And Control FTM0_C4SC 32 R W 0000_0000h 38 3 6 829 4003_8030 Channel n Value FTM0_C4V 32 R W 0000_0000h 38 3 7...

Страница 822: ...Output Control FTM0_SWOCTRL 32 R W 0000_0000h 38 3 26 865 4003_8098 FTM PWM Load FTM0_PWMLOAD 32 R W 0000_0000h 38 3 27 868 4003_9000 Status And Control FTM1_SC 32 R W 0000_0000h 38 3 3 826 4003_9004...

Страница 823: ...nels FTM1_COMBINE 32 R W 0000_0000h 38 3 14 842 4003_9068 Deadtime Insertion Control FTM1_DEADTIME 32 R W 0000_0000h 38 3 15 847 4003_906C FTM External Trigger FTM1_EXTTRIG 32 R W 0000_0000h 38 3 16 8...

Страница 824: ...7 832 4003_A03C Channel n Status And Control FTM2_C6SC 32 R W 0000_0000h 38 3 6 829 4003_A040 Channel n Value FTM2_C6V 32 R W 0000_0000h 38 3 7 832 4003_A044 Channel n Status And Control FTM2_C7SC 32...

Страница 825: ...0000h 38 3 22 860 4003_A088 FTM Fault Input Polarity FTM2_FLTPOL 32 R W 0000_0000h 38 3 23 861 4003_A08C Synchronization Configuration FTM2_SYNCONF 32 R W 0000_0000h 38 3 24 862 4003_A090 FTM Invertin...

Страница 826: ...s read only field is reserved and always has the value 0 7 TOF Timer Overflow Flag Set by hardware when the FTM counter passes the value in the MOD register The TOF bit is cleared by reading the SC re...

Страница 827: ...effect disables the FTM counter 01 System clock 10 Fixed frequency clock 11 External clock 2 0 PS Prescale Factor Selection Selects one of 8 division factors for the clock source selected by CLKS The...

Страница 828: ...he MOD register latches the value into a buffer The MOD register is updated with the value of its write buffer according to Registers updated from write buffers If FTMEN 0 this write coherency mechani...

Страница 829: ...Falling Edge Only 11 Capture on Rising or Falling Edge 01 01 Output Compare Toggle Output on match 10 Clear Output on match 11 Set Output on match 1X 10 Edge Aligned PWM High true pulses clear Output...

Страница 830: ...ble Detected Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1 Enabled Rising and falling edges Address Base address Ch offset 8d i where i 0d to 7d Bit 31 30 29 28 27 26...

Страница 831: ...en only when MODE WPDIS 1 4 MSA Channel Mode Select Used for further selections in the channel logic Its functionality is dependent on the channel mode See Table 38 7 This field is write protected It...

Страница 832: ...x_CnV field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 0 VAL Channel Value Captured FTM counter value of the in...

Страница 833: ...y one read of STATUS All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS Hardware sets the individual channel flags when an event occurs on the channel CHnF is cleared by...

Страница 834: ...the register description 0 No channel event has occurred 1 A channel event has occurred 5 CH5F Channel 5 Flag See the register description 0 No channel event has occurred 1 A channel event has occurr...

Страница 835: ...l enable bit for FTM specific features and the control bits used to configure Fault control mode and interrupt Capture Test mode PWM synchronization Write protection Channel output initialization Thes...

Страница 836: ...MOD CnV OUTMASK and FTM counter synchronization See PWM synchronization The PWMSYNC bit configures the synchronization when SYNCMODE is 0 0 No restrictions Software and hardware triggers can be used b...

Страница 837: ...dware or software triggers but not both at the same time otherwise unpredictable behavior is likely to happen The selection of the loading point CNTMAX and CNTMIN bits is intended to provide the updat...

Страница 838: ...1 input signal 0 Trigger is disabled 1 Trigger is enabled 4 TRIG0 PWM Synchronization Hardware Trigger 0 Enables hardware trigger 0 to the PWM synchronization Hardware trigger 0 occurs when a rising...

Страница 839: ...ding point is enabled 38 3 12 Initial State For Channels Output FTMx_OUTINIT Address Base address 5Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 840: ...Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs 0 The initialization value is 0 1 The initialization value is 1 1 CH1OI Channel 1 O...

Страница 841: ...lly 1 Channel output is masked It is forced to its inactive state 6 CH6OM Channel 6 Output Mask Defines if the channel output is masked or unmasked 0 Channel output is not masked It continues to opera...

Страница 842: ...continues to operate normally 1 Channel output is masked It is forced to its inactive state 38 3 14 Function For Linked Channels FTMx_COMBINE This register contains the control bits used to configure...

Страница 843: ...configuration of the dual edge capture bits This field applies only when DECAPEN 1 DECAP bit is cleared automatically by hardware if dual edge capture one shot mode is selected and when the capture o...

Страница 844: ...only when MODE WPDIS 1 0 The deadtime insertion in this pair of channels is disabled 1 The deadtime insertion in this pair of channels is enabled 19 DECAP2 Dual Edge Capture Mode Captures For n 4 Enab...

Страница 845: ...registers C n V and C n 1 V 0 The PWM synchronization in this pair of channels is disabled 1 The PWM synchronization in this pair of channels is enabled 12 DTEN1 Deadtime Enable For n 2 Enables the de...

Страница 846: ...rite protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in this pair of channels is enabled 5 SYNCEN0 Synchronization Enabl...

Страница 847: ...ombine feature for channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 Channels n and n 1 are independent 1 Channels n and n 1 are combined 38 3 15 Deadtime Ins...

Страница 848: ...to a possible 63 counts This field is write protected It can be written only when MODE WPDIS 1 38 3 16 FTM External Trigger FTMx_EXTTRIG This register Indicates when a channel trigger was generated E...

Страница 849: ...ated 6 INITTRIGEN Initialization Trigger Enable Enables the generation of the trigger when the FTM counter is equal to the CNTIN register 0 The generation of initialization trigger is disabled 1 The g...

Страница 850: ...2TRIG Channel 2 Trigger Enable Enables the generation of the channel trigger when the FTM counter is equal to the CnV register 0 The generation of the channel trigger is disabled 1 The generation of t...

Страница 851: ...4 POL4 Channel 4 Polarity Defines the polarity of the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity...

Страница 852: ...8 3 18 Fault Mode Status FTMx_FMS This register contains the fault detection flags write protection enable bit and the logic OR of the enabled fault inputs Address Base address 74h offset Bit 31 30 29...

Страница 853: ...the enabled fault inputs is 0 1 The logic OR of the enabled fault inputs is 1 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 FAULTF3 Fault Detection F...

Страница 854: ...ault input 1 A fault condition was detected at the fault input 0 FAULTF0 Fault Detection Flag 0 Set by hardware when fault control is enabled the corresponding fault input is enabled and a fault condi...

Страница 855: ...Channel 1 Input Filter Selects the filter value for the channel input The filter is disabled when the value is zero 3 0 CH0FVAL Channel 0 Input Filter Selects the filter value for the channel input T...

Страница 856: ...en MODE WPDIS 1 0 Fault input filter is disabled 1 Fault input filter is enabled 5 FFLTR1EN Fault Input 1 Filter Enable Enables the filter for the fault input This field is write protected It can be w...

Страница 857: ...only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fault input This field is write protected It can be written only when MODE WPDIS...

Страница 858: ...0 0 0 0 FTMx_QDCTRL field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 PHAFLTREN Phase A Input Filter Enable Enable...

Страница 859: ...used in the Quadrature Decoder mode 0 Phase A and phase B encoding mode 1 Count and direction encoding mode 2 QUADIR FTM Counter Direction In Quadrature Decoder Mode Indicates the counting direction...

Страница 860: ...the value 0 10 GTBEOUT Global Time Base Output Enables the global time base signal generation to other FTMs 0 A global time base signal generation is disabled 1 A global time base signal generation is...

Страница 861: ...0 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FLT3POL FLT2POL FLT1POL FLT0POL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_FLTPOL field descri...

Страница 862: ...fault 1 The fault input polarity is active low A 0 at the fault input indicates a fault 38 3 24 Synchronization Configuration FTMx_SYNCONF This register selects the PWM synchronization configuration S...

Страница 863: ...has the value 0 12 SWSOC Software output control synchronization is activated by the software trigger 0 The software trigger does not activate the SWOCTRL register synchronization 1 The software trig...

Страница 864: ...clock 1 CNTIN register is updated with its buffer value by the PWM synchronization 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 HWTRIGMODE Hardware T...

Страница 865: ...ble 0 Inverting is disabled 1 Inverting is enabled 0 INV0EN Pair Channels 0 Inverting Enable 0 Inverting is disabled 1 Inverting is enabled 38 3 26 FTM Software Output Control FTMx_SWOCTRL This regist...

Страница 866: ...tware Output Control Value 0 The software output control forces 0 to the channel output 1 The software output control forces 1 to the channel output 12 CH4OCV Channel 4 Software Output Control Value 0...

Страница 867: ...trol Enable 0 The channel output is not affected by software output control 1 The channel output is affected by software output control 3 CH3OC Channel 3 Software Output Control Enable 0 The channel o...

Страница 868: ...ved This read only field is reserved and always has the value 0 9 LDOK Load Enable Enables the loading of the MOD CNTIN and CV registers with the values of their write buffers 0 Loading updated values...

Страница 869: ...ching process 1 Include the channel in the matching process 1 CH1SEL Channel 1 Select 0 Do not include the channel in the matching process 1 Include the channel in the matching process 0 CH0SEL Channe...

Страница 870: ...ble the FTM counter After any MCU reset CLKS 1 0 0 0 so no clock source is selected The CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bits d...

Страница 871: ...ple of the prescaler counter and FTM counter FTM counter 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 2 3 3 1 1 1 1 1 1 1 1 1 selected input clock prescaler counter FTM counting is up PS 2 0 001 CNTIN 0x0000 MOD 0...

Страница 872: ...TOF bit set TOF bit 4 4 3 2 1 4 3 2 1 0 1 2 3 4 0 1 2 3 4 4 3 CNTIN 0xFFFC in two s complement is equal to 4 period of counting MOD CNTIN 0x0001 x period of FTM counter clock Figure 38 168 Example of...

Страница 873: ...requirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM counter is always equal to MOD an...

Страница 874: ...he final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until it returns to...

Страница 875: ...In this case 0 CPWM is generated 38 4 3 3 Free running counter If FTMEN 0 and MOD 0x0000 or MOD 0xFFFF the FTM counter is a free running counter In this case the FTM counter runs free from 0x0000 thro...

Страница 876: ...the TOF bit is set The NUMTOF 4 0 bits define the number of times that the FTM counter overflow should occur before the TOF bit to be set If NUMTOF 4 0 0x00 then the TOF bit is set at each FTM counte...

Страница 877: ...input capture the FTMxCHn pin is an edge sensitive input ELSnB ELSnA control bits determine which edge falling or rising triggers input capture event Note that the maximum frequency for the channel i...

Страница 878: ...1 Filter for Input Capture mode The filter function is only available on channels 0 1 2 and 3 First the input signal is synchronized by the system clock Following synchronization the input signal ente...

Страница 879: ...put The clock for the counter in the channel input filter is the system clock divided by 4 CHnFVAL 3 0 0010 binary value channel n input after the synchronizer counter filter output system clock divid...

Страница 880: ...also are reset 38 4 5 Output Compare mode The Output Compare mode is selected when DECAPEN 0 COMBINE 0 CPWMS 0 and MSnB MSnA 0 1 In Output Compare mode the FTM can generate timed pulses with programma...

Страница 881: ...ode when the match clears the channel output channel n output CHnF bit TOF bit CNT MOD 0x0005 CnV 0x0003 counter overflow channel n match counter overflow channel n match counter overflow 0 1 2 3 4 5...

Страница 882: ...aches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM If ELSnB ELSnA 1 0 then the channel n...

Страница 883: ...s different from zero the following EPWM signals can be generated 0 EPWM signal if CnV CNTIN EPWM signal between 0 and 100 if CNTIN CnV MOD 100 EPWM signal when CNTIN CnV or CnV MOD 38 4 7 Center Alig...

Страница 884: ...nB ELSnA 0 0 when the FTM counter reaches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM If...

Страница 885: ...do not need to generate a 100 duty cycle CPWM signal This is not a significant limitation because the resulting period is much longer than required for normal applications The CPWM mode must not be u...

Страница 886: ...in the generation of the channels n and n 1 output However if ELSnB ELSnA 0 0 then the channel n output is not controlled by FTM and if ELS n 1 B ELS n 1 A 0 0 then the channel n 1 output is not contr...

Страница 887: ...ELSnA X 1 MOD C n V CNTIN Figure 38 191 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSnB ELSnA 1 0 not fully 0 duty cycle channel...

Страница 888: ...C n V CNTIN and CNTIN C n 1 V MOD and C n 1 V is Almost Equal to MOD FTM counter 0 duty cycle channel n output with ELSnB ELSnA 1 0 100 duty cycle channel n output with ELSnB ELSnA X 1 C n V MOD CNTI...

Страница 889: ...hannel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle 0 duty cycle MOD Figure 38 196 Channel n output if C n V C n 1 V CNTIN FTM counter CNTIN channel n output with...

Страница 890: ...annel n output if CNTIN C n V MOD and CNTIN C n 1 V MOD and C n V C n 1 V FTM counter C n V channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 0 duty cycle 100 duty cycle MOD...

Страница 891: ...n 1 V CNTIN and CNTIN C n V MOD FTM counter channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle 0 duty cycle MOD C n V C n 1 V CNTIN Figure 38 201 Channel n outp...

Страница 892: ...3 Channel n output if C n 1 V MOD and CNTIN C n V MOD 38 4 8 1 Asymmetrical PWM In Combine mode the control of the PWM signal first edge when the channel n match occurs that is FTM counter C n V is in...

Страница 893: ...hannel n match Figure 38 204 Channel n 1 output in Complementary mode with ELSnB ELSnA 1 0 FTM counter channel n 1 match channel n 1 output with COMP 1 channel n 1 output with COMP 0 channel n output...

Страница 894: ...WMS bit that is If the selected mode is not CPWM then MOD register is updated after MOD register was written and the FTM counter changes from MOD to CNTIN If the FTM counter is at free running counter...

Страница 895: ...of the FTM counter the end of the prescaler counting If SYNCEN 1 then CnV register is updated by the C n V and C n 1 V register synchronization If the selected mode is not output compare and SYNCEN 1...

Страница 896: ...s written to it NOTE The HWTRIGMODE bit must be 1 only with enhanced PWM synchronization SYNCMODE 1 38 4 11 2 Software trigger A software trigger event occurs when 1 is written to the SYNC SWSYNC bit...

Страница 897: ...V In Up counting mode the boundary cycle is defined as when the counter wraps to its initial value CNTIN If in Up down counting mode then the boundary cycle is defined as when the counter turns from d...

Страница 898: ...lue This synchronization is enabled if FTMEN 1 The MOD register synchronization can be done by either the enhanced PWM synchronization SYNCMODE 1 or the legacy PWM synchronization SYNCMODE 0 However i...

Страница 899: ...wait hardware trigger n HWTRIGMODE bit clear TRIGn bit wait the next selected loading point update MOD with its buffer value update MOD with its buffer value HWRSTCNT bit Figure 38 209 MOD register s...

Страница 900: ...er is updated write 1 to TRIG0 bit TRIG0 bit trigger 0 event Figure 38 211 MOD synchronization with SYNCMODE 0 HWTRIGMODE 0 PWMSYNC 0 REINIT 0 and a hardware trigger was used If SYNCMODE 0 PWMSYNC 0 a...

Страница 901: ...MSYNC 0 REINIT 1 and a hardware trigger was used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place The SWSYN...

Страница 902: ...nization mechanism is the same as the MOD register synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCMODE 1 38 4...

Страница 903: ...igger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of system clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by hardware t...

Страница 904: ...SWSYNC bit software trigger event Figure 38 216 OUTMASK synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event O...

Страница 905: ...CTRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of system clock INVC 0 or by the enhanced PWM synchronization I...

Страница 906: ...bit rising edge of system clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGMODE...

Страница 907: ...OCTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of system clock yes 0 1 0 0 no 1 SWOC bit S...

Страница 908: ...el output from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event occurs synchronization event chan...

Страница 909: ...re trigger TRIGn bit 0 0 0 0 0 1 Figure 38 222 FTM counter synchronization flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits accord...

Страница 910: ...4 FTM counter synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a hardware trigger was used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled...

Страница 911: ...ted the channel n output behavior is changed to force high at the beginning of the PWM period force low at the channel n match and force high at the channel n 1 match See the following figure NOTE cha...

Страница 912: ...INVCTRL register synchronization INV m bit channel n output after the inverting channel n 1 output after the inverting INV m bit selects the inverting to the pair channels n and n 1 channel n output...

Страница 913: ...n OCV 1 and CH n 1 OCV 0 SWOCTRL register synchronization SWOCTRL register synchronization write to SWOCTRL register write to SWOCTRL register Figure 38 228 Example of software output control in Combi...

Страница 914: ...The DTPS 1 0 bits define the prescaler for the system clock and the DTVAL 5 0 bits define the deadtime modulo that is the number of the deadtime prescaler clocks The deadtime delay insertion ensures t...

Страница 915: ...e 38 229 Deadtime insertion with ELSnB ELSnA 1 0 POL n 0 and POL n 1 0 FTM counter channel n 1 match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n o...

Страница 916: ...Although in most cases the deadtime delay is not comparable to channels n and n 1 duty cycle the following figures show examples where the deadtime delay is comparable to the duty cycle FTM counter c...

Страница 917: ...sk The output mask can be used to force channels output to their inactive state through software For example to control a BLDC motor Any write to the OUTMASK register updates its write buffer The OUTM...

Страница 918: ...te 38 4 16 Fault control The fault control is enabled if FAULTM 1 0 0 0 FTM can have up to four fault inputs FAULTnEN bit where n 0 1 2 3 enables the fault input n and FFLTRnEN bit enables the fault i...

Страница 919: ...00 and FAULTnEN 1 then the fault input n signal is delayed 3 FFVAL 3 0 rising edges of the system clock that is the FAULTFn bit is set 4 FFVAL 3 0 rising edges of the system clock after a rising edge...

Страница 920: ...Automatic fault clearing If the automatic fault clearing is selected FAULTM 1 0 1 1 then the channels output disabled by fault control is again enabled when the fault input signal FAULTIN returns to...

Страница 921: ...the fault control with manual fault clearing and POLn 0 NOTE Figure 38 237 Fault control with manual fault clearing 38 4 16 3 Fault inputs polarity control The FLTjPOL bit selects the fault input j po...

Страница 922: ...nel n 1 Output 0 0 is forced to zero is forced to zero 0 1 is forced to zero is forced to one 1 0 is forced to one is forced to zero 1 1 is forced to one is forced to one The following table shows the...

Страница 923: ...output signal CH n OI CH n 1 OI COMP m INV m EN CH n OC CH n OCV CH n 1 OC CH n 1 OCV DTEN m CH n OM CH n 1 OM FAULTEN m POL n POL n 1 Figure 38 238 Priority of the features used at the generation of...

Страница 924: ...TRIG 1 CH4TRIG 1 CH5TRIG 1 the beginning of new PWM cycles MOD FTM counter C5V FTM counter C4V FTM counter C3V FTM counter C2V FTM counter C1V FTM counter C0V CNTIN a b c d Figure 38 239 Channel match...

Страница 925: ...ounting achieves the CNTIN register value CPWMS 0 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 initialization trigger write to CNT FTM counter system clock CNTIN 0x0000 MOD 0x000F Figure 38 241 I...

Страница 926: ...0x24 0x23 0x22 0x21 0x20 initialization trigger Figure 38 244 Initialization trigger is generated if the channel n is in Input Capture mode ICRST 1 and the selected input capture event occurs in the c...

Страница 927: ...T 1 CPWMS 0 CNTIN 0x0000 and MOD 0xFFFF FTM channel n configuration input capture mode DECAPEN 0 COMBINE 0 and MSnB MSnA 0 0 0x0300 0x78AC set CAPTEST clear CAPTEST write 0x78AC 0x1056 0x1053 0x1055 0...

Страница 928: ...4 24 Dual Edge Capture mode The Dual Edge Capture mode is selected if DECAPEN 1 This mode allows to measure a pulse width or period of the signal on the input of channel n of a channel pair The chann...

Страница 929: ...edge by channel n 1 is detected at channel n input In this mode a coherency mechanism ensures coherent data when the C n V and C n 1 V registers are read The only requirement is that C n V must be re...

Страница 930: ...s The latest captured values are always available in these registers even after the DECAP bit is cleared In this mode it is possible to clear only the CH n 1 F bit Therefore when the CH n 1 F bit is s...

Страница 931: ...r 4 9 11 12 13 14 9 10 7 8 15 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 19 20 22 24 Problem 1 channel n input 1 set DECAP not clear CH n F and clear CH n 1 F Problem 2 channel n input 1 set DECAP n...

Страница 932: ...F bit clear CH n F 1 8 12 22 24 11 19 21 23 Figure 38 248 Dual Edge Capture Continuous mode for positive polarity pulse width measurement 38 4 24 4 Period measurement If the channels n and n 1 are co...

Страница 933: ...C n 1 V registers are ready for reading channel n input after the filter DECAPEN bit C n 1 V FTM counter clear CH n 1 F problem 2 2 1 2 3 channel input DECAP bit set DECAPEN set DECAP 5 6 7 8 10 3 4...

Страница 934: ...V FTM counter clear CH n 1 F 2 1 2 3 channel input DECAP bit set DECAPEN set DECAP 5 6 7 8 10 3 4 6 5 Note The commands set DECAPEN set DECAP clear CH n F and clear CH n 1 F are made by the user 4 9 1...

Страница 935: ...ransferred to C n 1 V register when the C n V register is read In the following figure the read of C n V returns the FTM counter value when the event 1 occurred and the read of C n 1 V returns the FTM...

Страница 936: ...bits in FILTER0 register The phase B input filter is enabled by PHBFLTREN bit and this filter s value is defined by CH1FVAL 3 0 bits CH n 1 FVAL 3 0 bits in FILTER0 register Except for CH0FVAL 3 0 and...

Страница 937: ...A and B signals define the counting rate The FTM counter is updated when there is an edge either at the phase A or phase B signals If PHAPOL 0 and PHBPOL 0 then the FTM counter increment happens when...

Страница 938: ...FTM counter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fi...

Страница 939: ...rature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications phase A phase B FTM counter MOD CNTIN 0x0000...

Страница 940: ...avoid these oscillations 38 4 26 BDM mode When the chip is in BDM mode the BDMMODE 1 0 bits select the behavior of the FTM counter the CH n F bit the channels output and the writes to the MOD CNTIN a...

Страница 941: ...channels outputs are updated to the initial value except for channels in Output Compare mode In the channels outputs initialization the channel n output is forced to the CH n OI bit value when the val...

Страница 942: ...SEL 0 CH4SEL 1 CH5SEL 0 CH6SEL 1 CH7SEL 0 f LDOK 1 CH0SEL 1 CH1SEL 1 CH2SEL 1 CH3SEL 1 CH4SEL 1 CH5SEL 1 CH6SEL 1 CH7SEL 1 d e f b a FTM counter MOD FTM counter C7V FTM counter C6V FTM counter C5V FTM...

Страница 943: ...ailable on channel j output If CHjIE 1 then the channel j interrupt is generated when the channel j match occurs At the intermediate load neither the channels outputs nor the FTM counter are changed S...

Страница 944: ...dules the configuration of each FTM module should guarantee that its FTM counter starts counting as soon as the gtb_in signal is 1 The GTB feature does not provide continuous synchronization of FTM co...

Страница 945: ...er its value is updated to zero and the pins are not controlled by FTM See the table in the description of CnSC register After the reset the FTM should be configurated item 2 It is necessary to define...

Страница 946: ...here is a write to CNT register item 3 In this case use the software output control Software output control or the initialization Initialization to update the channel output to the selected value item...

Страница 947: ...re in the safe value Re Configuration FTM counter and channels to generation of periodic signals Disable the clock If the selected mode is Quadrature Decoder then disable this mode Examples of the re...

Страница 948: ...is necessary SWSOC 0 1 and SWOC 0 1 SW Synchronization for Inverting if it is necessary SWINVC 0 1 and INVC 0 1 SW Synchronization for SWOM always SWOM 1 No enable the SW Synchronization for write bu...

Страница 949: ...odule s instances see the chip configuration information The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels 39 1 1 Block diagram The following figure sh...

Страница 950: ...of PIT channels used in this MCU 39 1 2 Features The main features of this block are Ability of timers to generate DMA trigger pulses Ability of timers to generate interrupts Maskable interrupts Inde...

Страница 951: ...VAL1 32 R 0000_0000h 39 3 3 953 4003_7118 Timer Control Register PIT_TCTRL1 32 R W 0000_0000h 39 3 4 954 4003_711C Timer Flag Register PIT_TFLG1 32 R W 0000_0000h 39 3 5 954 4003_7120 Timer Load Value...

Страница 952: ...is reserved and always has the value 0 2 Reserved This field is reserved 1 MDIS Module Disable PIT section Disables the standard timers This field must be enabled before any other setup is done 0 Cloc...

Страница 953: ...expires To abort the current cycle and start a timer period with the new value the timer must be disabled and enabled again 39 3 3 Current Timer Value Register PIT_CVALn These registers indicate the c...

Страница 954: ...can decrement by 1 Timer 0 cannot be chained 0 Timer is not chained 1 Timer is chained to previous timer For example for Channel 2 if this field is set Timer 2 is chained to Timer 1 1 TIE Timer Inter...

Страница 955: ...scription This section provides the functional description of the module 39 4 1 General operation This section gives detailed information on the internal operation of the module Each timer can be used...

Страница 956: ...and then enabling the timer again See the following figure Timer enabled Disable timer p1 p1 Re enable timer Start value p1 Trigger event Set new load value p2 p2 p2 Figure 39 24 Modifying running tim...

Страница 957: ...evious timer has expired So if timer n 1 has counted down to 0 counter n will decrement the value by one This allows to chain some of the timers together to form a longer timer The first timer timer 0...

Страница 958: ...0 MHz Timers 1 and 2 are available An interrupt shall be raised every 1 minute The PIT module needs to be activated by writing a 0 to MCR MDIS The 100 MHz clock frequency equates to a clock period of...

Страница 959: ...counts PIT_TCTRL2 TIE enable Timer 2 interrupt PIT_TCTRL2 CHN chain Timer 2 to Timer 1 PIT_TCTRL2 TEN start Timer 2 Timer 1 PIT_LDVAL1 0x23C345FF setup Timer 1 for 600 000 000 cycles PIT_TCTRL1 TEN s...

Страница 960: ...Example configuration for chained timers K22F Sub Family Reference Manual Rev 3 7 2014 960 Freescale Semiconductor Inc...

Страница 961: ...vents allowing it to be used as a time of day counter 40 1 1 Features The features of the LPTMR module include 16 bit time counter or pulse counter with compare Optional interrupt can generate asynchr...

Страница 962: ...Table 40 2 LPTMR signal descriptions Signal I O Description LPTMR_ALTn I Pulse Counter Input pin 40 2 1 Detailed signal descriptions Table 40 3 LPTMR interface detailed signal descriptions Signal I O...

Страница 963: ...Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 TCF Timer Compare Flag TCF is set when the LPTMR is enabled and the CNR equals the CMR a...

Страница 964: ...abled 0 CNR is reset whenever TCF is set 1 CNR is reset on overflow 1 TMS Timer Mode Select Configures the mode of the LPTMR TMS must be altered only when the LPTMR is disabled 0 Time Counter mode 1 P...

Страница 965: ...r clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges 1010 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 ris...

Страница 966: ...When the LPTMR is enabled and the CNR equals the value in the CMR and increments TCF is set and the hardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigge...

Страница 967: ...four clocks The clock source must be enabled before the LPTMR is enabled NOTE The clock source selected may need to be configured to remain enabled in low power modes otherwise the LPTMR will not oper...

Страница 968: ...litch filter directly clocks the CNR When the LPTMR is first enabled the output of the glitch filter is asserted that is logic 1 for active high and logic 0 for active low The following table shows th...

Страница 969: ...aler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with glitch filter enabled T...

Страница 970: ...trigger will assert on each compare and deassert on the following increment of the CNR 40 4 7 LPTMR interrupt The LPTMR interrupt is generated whenever CSR TIE and CSR TCF are set CSR TCF is cleared b...

Страница 971: ...compensation that can correct errors between 0 12 ppm and 3906 ppm Register write protection Lock register requires VBAT POR or software reset to enable write access Access control registers require s...

Страница 972: ...68 kHz oscillator input I XTAL32 32 768 kHz oscillator output O RTC_CLKOUT 1 Hz square wave output O RTC_WAKEUP Wakeup for external device O 41 1 3 1 RTC clock output The clock to the seconds counter...

Страница 973: ...Time Prescaler Register RTC_TPR 32 R W 0000_0000h 41 2 2 974 4003_D008 RTC Time Alarm Register RTC_TAR 32 R W 0000_0000h 41 2 3 974 4003_D00C RTC Time Compensation Register RTC_TCR 32 R W 0000_0000h 4...

Страница 974: ...ons Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 0 TPR Time Prescaler Register When the time counter is enabled the TPR is rea...

Страница 975: ...Compensation Interval Register Configures the compensation interval in seconds from 1 to 256 to control how frequently the TCR should adjust the number of 32 768 kHz cycles in each second The value wr...

Страница 976: ...d descriptions Field Description 31 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 Reserved This field is reserved It must always be written to 0 13...

Страница 977: ...32kHz clock provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals 3 UM Update Mode Allows SR TCE to be written even when the Status Register is locked When set the S...

Страница 978: ...as the value 0 2 TAF Time Alarm Flag Time alarm flag is set when the TAR TAR equals the TSR TSR and the TSR TSR increments This bit is cleared by writing the TAR register 0 Time alarm has not occurred...

Страница 979: ...ed and writes complete as normal 5 SRL Status Register Lock After being cleared this bit can be set only by VBAT POR or software reset 0 Status Register is locked and writes are ignored 1 Status Regis...

Страница 980: ...t 1 If the wakeup pin is enabled then the wakeup pin will assert 6 5 Reserved This field is reserved 4 TSIE Time Seconds Interrupt Enable The seconds interrupt is an edge sensitive interrupt with a de...

Страница 981: ...Interrupt Enable Register Write After being cleared this bit is set only by system reset It is not affected by VBAT POR or software reset 0 Writes to the Interupt Enable Register are ignored 1 Writes...

Страница 982: ...the Time Alarm Register complete as normal 1 TPRW Time Prescaler Register Write After being cleared this bit is set only by system reset It is not affected by VBAT POR or software reset 0 Writes to th...

Страница 983: ...the Control Register are ignored 1 Reads to the Control Register complete as normal 3 TCRR Time Compensation Register Read After being cleared this bit is set only by system reset It is not affected...

Страница 984: ...The RTC also monitors the chip power supply and electrically isolates itself when the rest of the chip is powered down NOTE An attempt to access an RTC register except the access control registers re...

Страница 985: ...mended that two read accesses are performed and that software verifies that the same data was returned for both reads The time seconds register and time prescaler register can be written only when SR...

Страница 986: ...pensation value is used to adjust the number of clock cycles between 127 and 128 Cycles are added or subtracted from the prescaler register when the prescaler register equals 0x3FFF and then increment...

Страница 987: ...n be used to block write accesses to certain registers until the next VBAT POR or software reset Locking the Control register CR will disable the software reset Locking LR will block future updates to...

Страница 988: ...ted interrupt vector that is generated once a second and requires no software overhead there is no corresponding status flag to clear It is enabled in the RTC by the time seconds interrupt enable bit...

Страница 989: ...er 42 1 1 USB The USB is a cable bus that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals The attached peripherals share USB bandwidth through...

Страница 990: ...ble consumer electronic devices such as digital cameras and tablets to host PCs The On The Go OTG Supplement to the USB Specification extends USB to peer to peer application Using USB OTG technology c...

Страница 991: ...d points DMA or FIFO data stream interfaces Low power consumption On The Go protocol logic IRC48 with clock recovery is supported to eliminate the 48 MHz crystal It is used for USB device only impleme...

Страница 992: ...ximum throughput provided by USB Software should manage buffers for USBFS by updating the BDT when needed This allows USBFS to efficiently manage data transmission and reception while the microprocess...

Страница 993: ...on of data For this reason a USBFS core centric nomenclature is used to describe the direction of the data transfer between the USBFS core and USB RX or receive describes transfers that move data from...

Страница 994: ...ther it owns the BD and corresponding buffer in system memory To compute the entry point in to the BDT the BDT_PAGE registers is concatenated with the current endpoint and the TX and ODD fields to for...

Страница 995: ...Where the buffer resides in system memory The format for the BD is shown in the following figure Table 42 4 Buffer descriptor format 31 26 25 16 15 8 7 6 5 4 3 2 1 0 RSVD BC 10 bits RSVD OWN DATA0 1...

Страница 996: ...PID is written back to the BD by USBFS TOK_PID 3 If the OWN bit is also set the BD remains owned by USBFS indefinitely when written by USB it serves as the TOK_PID 3 bit 0 or 1 Bit 3 of the current t...

Страница 997: ...t the current token PID The current token PID is written back in to the BD by USBFS when a transfer completes The values written back are the token PID values from the USB specification 0x1h for an OU...

Страница 998: ...rrupt Generated TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated Figure 42 4 USB token transaction The USB has two sources for the DMA overrun error Memory Latency The memory latency may be too...

Страница 999: ...at represents the length of the clipped data actually written to memory From here the software can decide an appropriate course of action for future transactions such as stalling the endpoint cancelin...

Страница 1000: ...Page Register 3 USB0_BDTPAGE3 8 R W 00h 42 4 22 1018 4007_20C0 Endpoint Control register USB0_ENDPT0 8 R W 00h 42 4 23 1019 4007_20C4 Endpoint Control register USB0_ENDPT1 8 R W 00h 42 4 23 1019 4007_...

Страница 1001: ...USB Transceiver Control register 0 USB0_USBTRC0 8 R W 00h 42 4 27 1022 4007_2114 Frame Adjust Register USB0_USBFRMADJUST 8 R W 00h 42 4 28 1023 4007_2140 USB Clock recovery control USB0_CLK_RECOVER_C...

Страница 1002: ...D Write Reset 1 1 1 1 1 0 1 1 USBx_IDCOMP field descriptions Field Description 7 6 Reserved This field is reserved This read only field is reserved and always has the value 1 5 0 NID Ones complement o...

Страница 1003: ...rmine the event that triggers an interrupt Only bits that have changed since the last software read are set Writing a one to a bit clears the associated interrupt Address 4007_2000h base 10h offset 40...

Страница 1004: ...ved This read only field is reserved and always has the value 0 0 AVBUSCHG This bit is set when a change in VBUS is detected on an A device 42 4 6 OTG Interrupt Control register USBx_OTGICR Enables th...

Страница 1005: ...ield descriptions Field Description 7 ID Indicates the current state of the ID pin on the USB connector 0 Indicates a Type A cable is plugged into the USB connector 1 Indicates no cable is attached or...

Страница 1006: ...OTGCTL Controls the operation of VBUS and Data Line termination resistors Address 4007_2000h base 1Ch offset 4007_201Ch Bit 7 6 5 4 3 2 1 0 Read DPHIGH 0 DPLOW DMLOW 0 OTGEN 0 Write Reset 0 0 0 0 0 0...

Страница 1007: ...0 after a reset Address 4007_2000h base 80h offset 4007_2080h Bit 7 6 5 4 3 2 1 0 Read STALL ATTACH RESUME SLEEP TOKDNE SOFTOK ERROR USBRST Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0...

Страница 1008: ...SBRST This bit is set when the USB Module has decoded a valid USB reset This informs the processor that it should write 0x00 into the address register and enable endpoint 0 USBRST is set after a USB r...

Страница 1009: ...of this register are logically OR d together and the result placed in the ERROR bit of the ISTAT register After an interrupt bit has been set it may only be cleared by writing a one to the respective...

Страница 1010: ...s be an integral number of bytes If the data field was not an integral number of bytes this bit is set 2 CRC16 This bit is set when a data packet is rejected due to a CRC16 error 1 CRC5EOF This error...

Страница 1011: ...the BTOERR interrupt 1 Enables the BTOERR interrupt 3 DFN8EN DFN8 Interrupt Enable 0 Disables the DFN8 interrupt 1 Enables the DFN8 interrupt 2 CRC16EN CRC16 Interrupt Enable 0 Disables the CRC16 inte...

Страница 1012: ...KDNE bit in the ISTAT register causes the SIE to update STAT with the contents of the next STAT value If the data in the STAT holding register is valid the SIE immediately reasserts to TOKDNE interrup...

Страница 1013: ...set USB peripherals This control signal is only valid in Host mode HOSTMODEEN 1 Software must set RESET to 1 for the required amount of time and then clear it to 0 to end reset signaling For more info...

Страница 1014: ...es active or the USB module decodes a USB reset signal This action initializes the Address register to decode address 0x00 as required by the USB specification Address 4007_2000h base 98h offset 4007_...

Страница 1015: ...is reserved This read only field is reserved and always has the value 0 42 4 17 Frame Number register Low USBx_FRMNUML The Frame Number registers low and high contain the 11 bit frame number These reg...

Страница 1016: ...peripheral it writes the TOKEN type and endpoint to this register After this register has been written the USB module begins the specified USB transaction to the address contained in the address regi...

Страница 1017: ...acket transactions This register must be set to a value that ensures that other packets are not actively being transmitted when the SOF time counts to zero When the SOF counter reaches the threshold v...

Страница 1018: ...er Descriptor Table resides in system memory 42 4 22 BDT Page Register 3 USBx_BDTPAGE3 Contains an 8 bit value used to compute the address where the current Buffer Descriptor Table BDT resides in syst...

Страница 1019: ...define if an endpoint is enabled and define the direction of the endpoint The endpoint enable direction control is defined in the following table Table 42 97 Endpoint enable and direction control EPCT...

Страница 1020: ...hen set enables the endpoint for TX transfers See Table 42 31 1 EPSTALL When set this bit indicates that the endpoint is called This bit has priority over all other control bits in the EndPoint Enable...

Страница 1021: ...pulldown disabled 1 D pulldown enabled 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 DMPD Provides observability of the D Pulldown enable at the USB...

Страница 1022: ...4 Read 0 USBRESMEN 0 Write USBRESET Reset 0 0 0 0 Bit 3 2 1 0 Read 0 USB_CLK_ RECOVERY_INT SYNC_DET USB_RESUME_INT Write Reset 0 0 0 0 USBx_USBTRC0 field descriptions Field Description 7 USBRESET USB...

Страница 1023: ...cating that the frequency trim calculated is out of the adjustment range of the IRC48M output clock To clear this bit after it has been set Write 0xFF to register USB_CLK_RECOVER_INT_STATUS 1 SYNC_DET...

Страница 1024: ...cking phase The step to fine tune the IRC 48Mhz by adjusting the trim fine value is different during these two phases The step in rough phase is larger than that in tracking phase Switch back to rough...

Страница 1025: ...criptions Field Description 7 2 Reserved This field is reserved 1 IRC_EN IRC48M enable This bit is used to enable the on chip IRC48Mhz module to generate clocks for crystal less USB It can be used for...

Страница 1026: ...n 7 5 Reserved This field is reserved Should always be written as 0 4 OVF_ERROR_ EN Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT 0 The interrupt will be...

Страница 1027: ...palmtop computer with the obvious advantages of easier interaction Host mode is intended for use in handheld portable devices to allow easy connection to simple HID class devices such as printers and...

Страница 1028: ...tor changing the state of DPLUS or DMINUS from 0 to 1 SE0 to J or K state 4 Check the state of the JSTATE and SE0 bits in the control register If the connecting device is low speed JSTATE bit is 0 set...

Страница 1029: ...Device Framework http www usb org developers docs 7 To initiate the data phase of the setup transaction that is get the data for the GET DEVICE DESCRIPTOR command set up a buffer in memory for the da...

Страница 1030: ...ally there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant 2 Write 0x1D to ENDPT0 register to enable transmit and receive tra...

Страница 1031: ...tocol SRP API calls are provided to give access to the OTG protocol control signals and include the OTG capabilities in the device application The following state machines show the OTG operations invo...

Страница 1032: ...d or the A device cannot support the current required from the B device Go to A_WAIT_VFALL Turn off DRV_VBUS If A_VBUS_VLD interrupt Go to A_WAIT_BCON A_WAIT_BCON After 200 ms without Attach or ID Int...

Страница 1033: ...rrupt Go to A_WAIT_VFALL Turn off DRV_VBUS If 3 200 ms of Bus Idle Go to A_WAIT_BCON Turn on Host mode A_WAIT_VFALL If ID Interrupt or A_SESS_VLD b_conn Go to A_IDLE 42 7 2 OTG dual role B device oper...

Страница 1034: ...goes away the host doesn t support us Go to B_IDLE Go to B_IDLE If 3 125 ms expires or if a Resume occurs Go to B_PERIPHERAL B_HOST If ID Interrupt or B_SESS_VLD Interrupt If the cable changes or if...

Страница 1035: ...SIM_SOPT2 USBSRC 1b For chip specific details see the USB FS OTG controller clocking information in the Clock Distribution chapter Chapter 42 Universal Serial Bus Full Speed OTG Controller USBFSOTG K...

Страница 1036: ...Device mode IRC48 operation K22F Sub Family Reference Manual Rev 3 7 2014 1036 Freescale Semiconductor Inc...

Страница 1037: ...input power supply varying from 2 7 V to 5 5 V It consists of one 3 3 V power channel When the input power supply is below 3 6 V the regulator goes to pass through mode The following figure shows the...

Страница 1038: ...but a switch disconnects its output from the external pin In STANDBY mode the RUN regulator is disabled and the STANDBY regulator output is connected to the external pin Internal power mode signals co...

Страница 1039: ...or is disabled and the standby regulator is active The switch connecting the STANDBY regulator output to the external pin is closed SHUTDOWN The module is disabled The regulator is enabled by default...

Страница 1040: ...USB Voltage Regulator Module Signal Descriptions K22F Sub Family Reference Manual Rev 3 7 2014 1040 Freescale Semiconductor Inc...

Страница 1041: ...ces see the chip configuration information The serial peripheral interface SPI module provides a synchronous serial bus for communication between an MCU and an external peripheral device 44 1 1 Block...

Страница 1042: ...duplex three wire synchronous transfers Master mode Slave mode Data streaming operation in Slave mode with continuous slave selection Buffered transmit operation using the transmit first in first out...

Страница 1043: ...p selects PCSes with external demultiplexer DMA support for adding entries to TX FIFO and removing entries from RX FIFO TX FIFO is not full TFFF RX FIFO is not empty RFDF Interrupt conditions End of Q...

Страница 1044: ...can reside in system RAM external to the module Data transfers between the queues and the module FIFOs are accomplished by a DMA controller or host CPU The following figure shows a system example wit...

Страница 1045: ...als are controlled by the module and configured as outputs SCK SOUT PCS x 44 1 4 2 Slave Mode Slave mode allows the module to communicate with SPI bus masters In this mode the module responds to exter...

Страница 1046: ...nal descriptions This table describes the signals on the boundary of the module that may connect off chip in alphabetical order Table 44 1 Module signal descriptions Signal Master mode Slave mode I O...

Страница 1047: ...ta transmitted by the module Peripheral Chip Select Strobe O Used only when the peripheral chip select strobe is enabled MCR PCSSE Strobes an off module peripheral chip select demultiplexer which deco...

Страница 1048: ...and Transfer Attributes Register In Master Mode SPI0_CTAR0 32 R W 7800_0000h 44 3 3 1053 4002_C00C Clock and Transfer Attributes Register In Slave Mode SPI0_CTAR0_SLAVE 32 R W 7800_0000h 44 3 4 1058 4...

Страница 1049: ...Mode SPI1_CTAR1 32 R W 7800_0000h 44 3 3 1053 4002_D02C Status Register SPI1_SR 32 R W See section 44 3 5 1060 4002_D030 DMA Interrupt Request Select and Enable Register SPI1_RSER 32 R W 0000_0000h 4...

Страница 1050: ...OOE 0 PCSIS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DOZE MDIS DIS_ TXF DIS_ RXF 0 0 SMPL_PT 0 Reserved Reserved HALT W CLR_TXF CLR_RXF Reset 0 1 0 0 0 0 0 0...

Страница 1051: ...PCS Strobe signal 24 ROOE Receive FIFO Overflow Overwrite Enable In the RX FIFO overflow condition configures the module to ignore the incoming serial data or overwrite existing data If the RX FIFO i...

Страница 1052: ...This bit can only be written when the MDIS bit is cleared 0 RX FIFO is enabled 1 RX FIFO is disabled 11 CLR_TXF Clear TX FIFO Flushes the TX FIFO Writing a 1 to CLR_TXF clears the TX FIFO Counter The...

Страница 1053: ...ield Description 31 16 SPI_TCNT SPI Transfer Counter Counts the number of SPI transfers the module makes The SPI_TCNT field increments every time the last bit of an SPI frame is transmitted A value wr...

Страница 1054: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIx_CTARn field descriptions Field Description 31 DBR Double Baud Rate Doubles the effective baud rate of the Serial Communications Clock SCK This field is used...

Страница 1055: ...sful communication between serial devices the devices must have identical clock phase settings In Continuous SCK mode the bit value is ignored and the transfers are done as if the CPHA bit is set to 1...

Страница 1056: ...uency of the SCK The protocol clock is divided by the prescaler value before the baud rate selection takes place See the BR field description for details on how to compute the baud rate 00 Baud Rate P...

Страница 1057: ...PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame In the Continuous Serial Communications Clock operation the DT value is fixed to one SCK clock period The...

Страница 1058: ...d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R FMSZ CPOL CPHA 0 Reserved Reserved W Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserv...

Страница 1059: ...both master and slave mode For successful communication between serial devices the devices must have identical clock phase settings In Continuous SCK mode the bit value is ignored and the transfers ar...

Страница 1060: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TXCTR TXNXTPTR RXCTR POPNXTPTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIx_SR field descriptions Field Description 31 TCF Transfer Complete Flag Indicates that...

Страница 1061: ...e to request more entries to be added to the TX FIFO The TFFF bit is set while the TX FIFO is not full The TFFF bit can be cleared by writing 1 to it or by acknowledgement from the DMA controller to t...

Страница 1062: ...remented every time an SPI command is executed and the SPI data is transferred to the shift register 11 8 TXNXTPTR Transmit Next Pointer Indicates which TX FIFO entry is transmitted during the next tr...

Страница 1063: ...nable Enables TCF flag in the SR to generate an interrupt request 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled 30 Reserved This field is reserved This read only field is...

Страница 1064: ...e FIFO Overflow Request Enable Enables the RFOF flag in the SR to generate an interrupt request 0 RFOF interrupt requests are disabled 1 RFOF interrupt requests are enabled 18 Reserved This field is r...

Страница 1065: ...t update the FIFO Therefore any reads performed while the module is disabled return the last PUSHR write performed while the module was still enabled Address Base address 34h offset Bit 31 30 29 28 27...

Страница 1066: ...r Counter Clears the TCNT field in the TCR register The TCNT field is cleared before the module starts transmitting the current SPI frame 0 Do not clear the TCR TCNT field 1 Clear the TCR TCNT field 2...

Страница 1067: ...ociated SPI command 44 3 9 POP RX FIFO Register SPIx_POPR POPR is used to read the RX FIFO Eight or sixteen bit read accesses to the POPR have the same effect on the RX FIFO as 32 bit read accesses A...

Страница 1068: ...ts the transfer attributes for the SPI data In Slave mode the TXDATA contains 16 MSB bits of the SPI data to be shifted out 15 0 TXDATA Transmit Data Contains the SPI data to be shifted out 44 3 11 Re...

Страница 1069: ...me basis by setting a field in the SPI command See Clock and Transfer Attributes Register In Master Mode SPI_CTARn for information on the fields of CTAR registers Typical master to slave connections a...

Страница 1070: ...no transfers are responded to in Slave mode The Stopped state is also a safe state for writing the various configuration registers of the module without causing undetermined results In the Running st...

Страница 1071: ...sfers initiated by a bus master external to it and the SPI command field space is reserved 44 4 2 1 Master mode In SPI Master mode the module initiates the serial transfers by controlling the SCK and...

Страница 1072: ...g of SPI data The number of entries in the TX FIFO is device specific SPI data is added to the TX FIFO by writing to the Data Field of module PUSH FIFO Register PUSHR TX FIFO entries can only be remov...

Страница 1073: ...The RX FIFO functions as a buffer for data received on the SIN pin The RX FIFO holds 4 received SPI data frames The number of entries in the RX FIFO is device specific SPI data is added to the RX FIF...

Страница 1074: ...rom the RX FIFO by reading the module POP RX FIFO Register POPR A read of the POPR decrements the RX FIFO Counter by one Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO Counter...

Страница 1075: ...ncy used to drive this module in the device 44 4 3 2 PCS to SCK Delay tCSC The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge See Figure 44 72 for an ill...

Страница 1076: ...tween negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame See Figure 44 72 for an illustration of the Delay after Transfer The PDT and DT fields in the CTARx...

Страница 1077: ...CK field in the CTAR based on the following formula P At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the CTAR based on the following formu...

Страница 1078: ...bus slave does not control the SCK signal in Slave mode the values of CPOL and CPHA must be identical to the master device settings to ensure proper transmission In SPI Slave mode only CTAR0 is used...

Страница 1079: ...initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate peripheral chip select signals to the slave device The slave responds by placing its first data bit...

Страница 1080: ...t 4 Bit 3 Bit 2 Bit 1 LSB first LSBFE 1 LSB Figure 44 73 Module transfer timing diagram MTFE 0 CPHA 1 FMSZ 8 The master initiates the transfer by asserting the PCS signal to the slave After the tCSC d...

Страница 1081: ...are selected by the PCSISn bits in the MCR The following timing diagram is for two four bit transfers with CPHA 1 and CONT 0 PCSx SCK Master SIN tCSC PCS to SCK dela t ASC After SCK delay SCK CPOL 0 S...

Страница 1082: ...master deasserts the PCSn at end of transmission of the last frame PUSHR CONT must be deasserted before asserting MCR HALT in master mode This will make sure that the PCSn signals are deasserted Asser...

Страница 1083: ...s used In all configurations the currently selected CTAR remains in use until the start of a frame with a different CTAR specified or the Continuous SCK mode is terminated It is recommended to keep th...

Страница 1084: ...ions include Continuous SCK with CONT bit set but no data in the TX FIFO Continuous SCK with CONT bit set and entering Stopped state refer to Start and Stop of module transfers Continuous SCK with CON...

Страница 1085: ...s several conditions that can generate only interrupt requests and two conditions that can generate interrupt or DMA requests The following table lists these conditions Table 44 104 Interrupt and DMA...

Страница 1086: ...s generated NOTE TFFF flag clears automatically when DMA is used to fill TX FIFO To clear TFFF when not using DMA follow these steps for every PUSH performed using CPU to fill TX FIFO 1 Wait until TFF...

Страница 1087: ...e RSER must be set for the interrupt request to be generated Depending on the state of the ROOE bit in the MCR the data from the transfer that generated the overflow is either ignored or shifted in to...

Страница 1088: ...ct when the module is in the Module Disable mode Reading the RX FIFO Pop Register does not change the state of the RX FIFO Similarly writing to the PUSHR Register does not change the state of the TX F...

Страница 1089: ...new queues 8 Flush TX FIFO by writing a 1 to the CLR_TXF bit in the MCR Flush RX FIFO by writing a 1 to the CLR_RXF bit in the MCR 9 Clear transfer count either by setting CTCNT bit in the command wo...

Страница 1090: ...E The clock frequency mentioned above is given as an example in this chapter See the clocking chapter for the frequency used to drive this module in the device Table 44 105 Baud rate values bps Baud r...

Страница 1091: ...2 8 s 17 9 s 512 5 1 s 15 4 s 25 6 s 35 8 s 1024 10 2 s 30 7 s 51 2 s 71 7 s 2048 20 5 s 61 4 s 102 4 s 143 4 s 4096 41 0 s 122 9 s 204 8 s 286 7 s 8192 81 9 s 245 8 s 409 6 s 573 4 s 16384 163 8 s 49...

Страница 1092: ...44 78 TX FIFO pointers and counter 44 5 6 1 Address Calculation for the First in Entry and Last in Entry in the TX FIFO The memory address of the first in entry in the TX FIFO is computed by the foll...

Страница 1093: ...g equation The memory address of the last in entry in the RX FIFO is computed by the following equation RX FIFO Base Base address of RX FIFO RXCTR RX FIFO counter POPNXTPTR Pop Next Pointer RX FIFO De...

Страница 1094: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 1094 Freescale Semiconductor Inc...

Страница 1095: ...be connected are limited by a maximum bus capacitance of 400 pF The I2C module also complies with the System Management Bus SMBus Specification version 2 45 1 1 Features The I2C module has the followi...

Страница 1096: ...he basic mode of operation To conserve power in this mode disable the module Wait mode The module continues to operate when the core is in Wait mode and can provide a wakeup interrupt Stop mode The mo...

Страница 1097: ...ure 45 1 I2C Functional block diagram 45 2 I2C signal descriptions The signal properties of I2C are shown in the table found here Table 45 1 I2C signal descriptions Signal Description I O SCL Bidirect...

Страница 1098: ...6_600A I2C SCL Low Timeout Register High I2C0_SLTH 8 R W 00h 45 3 11 1109 4006_600B I2C SCL Low Timeout Register Low I2C0_SLTL 8 R W 00h 45 3 12 1110 4006_7000 I2C Address Register 1 I2C1_A1 8 R W 00h...

Страница 1099: ...1 0 Read MULT ICR Write Reset 0 0 0 0 0 0 0 0 I2Cx_F field descriptions Field Description 7 6 MULT Multiplier Factor Defines the multiplier factor mul This factor is used along with the SCL divider to...

Страница 1100: ...e For example if the I2C module clock speed is 8 MHz the following table shows the possible hold time values with different ICR and MULT selections to achieve an I2C baud rate of 100 kbit s MULT ICR H...

Страница 1101: ...f FACK is cleared or the current receiving byte if FACK is set 1 No acknowledge signal is sent to the bus on the following receiving data byte if FACK is cleared or the current receiving data byte if...

Страница 1102: ...data register in transmit mode 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed As A Slave This bit is set by one of the following conditions The calling address matches the programmed prim...

Страница 1103: ...iting 1 to it such as in the interrupt routine One of the following events can set this bit One byte transfer including ACK NACK bit completes if FACK is 0 An ACK or NACK is sent on the bus by writing...

Страница 1104: ...e Data register does not initiate the receive Reading the Data register returns the last byte received while the I2C module is configured in master receive or slave receive mode The Data register does...

Страница 1105: ...hen this bit is set a slave address matching occurs for any address greater than the value of the A1 register and less than or equal to the value of the RA register 0 Range mode disabled No address ma...

Страница 1106: ...CF bit after the MCU wakes from the stop mode 0 Stop holdoff is disabled The MCU s entry to stop mode is not gated 1 Stop holdoff is enabled 6 STOPF I2C Bus Stop Detect Flag Hardware sets this bit whe...

Страница 1107: ...rol and Status register I2Cx_SMB NOTE When the SCL and SDA signals are held high for a length of time greater than the high timeout period the SHTF1 flag sets Before reaching this threshold while the...

Страница 1108: ...Clock Select Selects the clock source of the timeout counter 0 Timeout counter counts at the frequency of the I2C module clock 64 1 Timeout counter counts at the frequency of the I2C module clock 3 S...

Страница 1109: ...used by the SMBus This field is used on the device default address or other related addresses 0 Reserved This field is reserved This read only field is reserved and always has the value 0 45 3 11 I2C...

Страница 1110: ...s a serial data line SDA and a serial clock line SCL for data transfers All devices connected to it must have open drain or open collector outputs A logic AND function is exercised on both lines with...

Страница 1111: ...igh to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer might contain several bytes of data and brings all slaves out of their idle s...

Страница 1112: ...s signaled from the receiving device by pulling SDA low at the ninth clock In summary one complete data transfer needs nine clock pulses If the slave receiver does not acknowledge the master in the ni...

Страница 1113: ...ase the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets a status bit to indicate the loss of arbitration 45 4 1 7 Clock synchronization Because wire AND...

Страница 1114: ...w a slave can drive SCL low for the required period and then release it If the slave s SCL low period is greater than the master s SCL low period the resulting SCL bus signal s low period is stretched...

Страница 1115: ...7 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129...

Страница 1116: ...7 bits 11110 AD10 AD9 R W 0 A1 Slave address second byte AD 8 1 A2 Data A Data A A P After the master transmitter has sent the first byte of the 10 bit address the slave receiver sees an I2C interrupt...

Страница 1117: ...g process It provides a 7 bit address If the ADEXT bit is set AD 10 8 in Control Register 2 participates in the address matching process It extends the I2C primary slave address to a 10 bit address Ad...

Страница 1118: ...and be able to receive a new START condition within the timeframe of TTIMEOUT MAX SMBus defines a clock low timeout TTIMEOUT of 35 ms specifies TLOW SEXT as the cumulative clock low extend time for a...

Страница 1119: ...intervals TLOW SEXT and TLOW MEXT When in master mode the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is defined as STAR...

Страница 1120: ...o acknowledge its own address as a mechanism to detect the presence of a removable device such as a battery or docking station on the bus In addition to indicating a slave device busy condition SMBus...

Страница 1121: ...IICIF IICIE Arbitration lost ARBL IICIF IICIE I2C bus stop detection STOPF IICIF IICIE SSIE I2C bus start detection STARTF IICIF IICIE SSIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA lo...

Страница 1122: ...r more masters try to control the bus at the same time the relative priority of the contending masters is determined by a data arbitration procedure The I2C module asserts the arbitration lost interru...

Страница 1123: ...The width of the glitch to absorb can be specified in terms of the number of half I2C module clock cycles A single Programmable Input Glitch Filter control register is provided Effectively any down u...

Страница 1124: ...DMAEN bit is cleared and the IICIE bit is set an interrupt condition generates an interrupt request If the DMAEN bit is set and the IICIE bit is set an interrupt condition generates a DMA request ins...

Страница 1125: ...smit data 4 Initialize RAM variables used to achieve the routine shown in the following figure 5 Write Control Register 1 to enable TX 6 Write Control Register 1 to enable MST master mode 7 Write Data...

Страница 1126: ...rom Data reg N Y N N N N N N Y Y Y Y Y read N write N Y Rx Tx Rx Tx Y N Address transfer see note 1 Data transfer see note 2 N Y Y Y Notes 1 If general call is enabled check to determine if the receiv...

Страница 1127: ...o Data reg Clear IICIF Notes 1 If general call or SIICAEN is enabled check to determine if the received address is a general call address 0x00 or an SMBus device default address In either case they mu...

Страница 1128: ...Initialization application information K22F Sub Family Reference Manual Rev 3 7 2014 1128 Freescale Semiconductor Inc...

Страница 1129: ...es Full duplex operation Standard mark space non return to zero NRZ format Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse width 13 bit baud rate selection with 32 fract...

Страница 1130: ...try threshold Support for 11 and 12 ETU transfers Detection of initial packet and automated transfer parameter programming Interrupt driven operation with seven ISO 7816 specific interrupts Wait time...

Страница 1131: ...l mode of operation 46 1 2 2 Wait mode UART operation in the Wait mode depends on the state of the C1 UARTSWAI field If C1 UARTSWAI is cleared and the CPU is in Wait mode the UART operates normally If...

Страница 1132: ...abled The UART operation resumes after an external interrupt brings the CPU out of Stop mode Bringing the CPU out of Stop mode by reset aborts any ongoing transmission or reception and resets the UART...

Страница 1133: ...me can deassert asynchronously to the other input signals RXD I Receive data Serial data input to receiver State meaning Whether RXD is interpreted as a 1 or 0 depends on the bit encoding method along...

Страница 1134: ...a Register UART0_ED 8 R 00h 46 3 13 1153 4006_A00D UART Modem Register UART0_MODEM 8 R W 00h 46 3 14 1154 4006_A00E UART Infrared Register UART0_IR 8 R W 00h 46 3 15 1155 4006_A010 UART FIFO Parameter...

Страница 1135: ...W 06h 46 3 37 1172 4006_A03F UART 7816 Wait Parameter Register C UART0_WP7816C_T1 8 R W 0Bh 46 3 38 1172 4006_B000 UART Baud Rate Registers High UART1_BDH 8 R W 00h 46 3 1 1138 4006_B001 UART Baud Ra...

Страница 1136: ...1_IS7816 8 R W 00h 46 3 25 1164 4006_B01B UART 7816 Wait Parameter Register UART1_WP7816 8 R W 00h 46 3 26 1166 4006_B01C UART 7816 Wait N Register UART1_WN7816 8 R W 00h 46 3 27 1166 4006_B01D UART 7...

Страница 1137: ...006_C00A UART Control Register 4 UART2_C4 8 R W 00h 46 3 11 1151 4006_C00B UART Control Register 5 UART2_C5 8 R W 00h 46 3 12 1152 4006_C00C UART Extended Data Register UART2_ED 8 R 00h 46 3 13 1153 4...

Страница 1138: ...RT 7816 Wait Parameter Register A UART2_WP7816A_T1 8 R W 00h 46 3 34 1170 4006_C03D UART 7816 Wait Parameter Register B UART2_WP7816B_T0 8 R W 14h 46 3 35 1171 4006_C03D UART 7816 Wait Parameter Regis...

Страница 1139: ...aud rate generator is disabled until C2 TE or C2 RE is set for the first time after reset The baud rate generator is disabled when SBR 0 Writing to BDH has no effect without writing to BDL because wri...

Страница 1140: ...ted from the UART and the transmitter output is internally connected to the receiver input The transmitter and the receiver must be enabled to use the loop function 0 Normal operation 1 Loop mode wher...

Страница 1141: ...its In idle line wakeup an idle character is recognized at anytime the receiver sees 10 11 or 12 1s depending on the M PE and C4 M10 fields 0 Idle character bit count starts after start bit 1 Idle cha...

Страница 1142: ...rupt requests 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled 3 TE Transmitter Enable Enables the UART transmitter TE can be used to queue an idle preamble by clearing and then se...

Страница 1143: ...es inputs to the MCU for generation of UART interrupts or DMA requests This register can also be polled by the MCU to check the status of its fields To clear a flag the status register should be read...

Страница 1144: ...idle logic 1 TC is cleared by reading S1 with TC set and then doing one of the following When C7816 ISO_7816E is set enabled this field is set after any NACK signal has been received but prior to any...

Страница 1145: ...BKDE is enabled and a LIN Break is detected the OR field asserts if S2 LBKDIF is not cleared before the next data character is received In 7816 mode it is possible to configure a NACK to be returned b...

Страница 1146: ...sts Also this register can be polled by the MCU to check the status of these bits This register can be read or written at any time with the exception of the MSBF and RXINV bits which should be changed...

Страница 1147: ...V inverts the RxD input for data bits start and stop bits break and idle When C7816 ISO7816E is set enabled only the data bits and the parity bit are inverted 0 Receive data is not inverted 1 Receive...

Страница 1148: ...ter To read the 9th bit read the value of UARTx_C3 R8 then read the UARTx_D register 6 T8 Transmit Bit 8 T8 is the ninth data bit transmitted when the UART is configured for 9 bit data format that is...

Страница 1149: ...and parity bit are inverted 0 Transmit data is not inverted 1 Transmit data is inverted 3 ORIE Overrun Error Interrupt Enable Enables the overrun error flag S1 OR to generate interrupt requests 0 OR i...

Страница 1150: ...ritten first and then the new data on data bus is stored in D the temporary value written by the last write to C3 T8 gets stored in the C3 T8 register Address Base address 7h offset Bit 7 6 5 4 3 2 1...

Страница 1151: ...it 7 6 5 4 3 2 1 0 Read MAEN1 MAEN2 M10 BRFA Write Reset 0 0 0 0 0 0 0 0 UARTx_C4 field descriptions Field Description 7 MAEN1 Match Address Mode Enable 1 See Match address operation for more informat...

Страница 1152: ...add more timing resolution to the average baud frequency in increments of 1 32 See Baud rate generation for more information 46 3 12 UART Control Register 5 UARTx_C5 Address Base address Bh offset Bi...

Страница 1153: ...re stored with a received dataword This register may be read at any time but contains valid data only if there is a dataword in the receive FIFO NOTE The data contained in this register represents add...

Страница 1154: ...0 0 0 0 0 UARTx_MODEM field descriptions Field Description 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 RXRTSE Receiver request to send enable All...

Страница 1155: ...nd a character If CTS is asserted the character is sent If CTS is deasserted the signal TXD remains in the mark state and transmission is delayed until CTS is asserted Changes in CTS as a character is...

Страница 1156: ...nable When this field is set the built in FIFO structure for the transmit buffer is enabled The size of the FIFO structure is indicated by TXFIFOSIZE If this field is not set the transmit buffer opera...

Страница 1157: ...FIFO Buffer depth 32 datawords 101 Receive FIFO Buffer depth 64 datawords 110 Receive FIFO Buffer depth 128 datawords 111 Reserved 46 3 17 UART FIFO Control Register UARTx_CFIFO This register provide...

Страница 1158: ...interrupt to the host 1 TXOF flag generates an interrupt to the host 0 RXUFE Receive FIFO Underflow Interrupt Enable When this field is set the RXUF flag generates an interrupt to the host 0 RXUF fla...

Страница 1159: ...interrupt will be issued to the host only if CFIFO TXOFE is set This flag is cleared by writing a 1 0 No transmit buffer overflow has occurred since the last time the flag was cleared 1 At least one...

Страница 1160: ..._TCFIFO field descriptions Field Description 7 0 TXCOUNT Transmit Counter The value in this register indicates the number of datawords that are in the transmit FIFO buffer If a dataword is being trans...

Страница 1161: ...XCOUNT Receive Counter The value in this register indicates the number of datawords that are in the receive FIFO buffer If a dataword is being received that is in the receive shift register it is not...

Страница 1162: ...lid initial character If an invalid initial character is identified and ANACK is set a NACK is sent All received data is discarded and error flags blocked S1 NF S1 OR S1 FE S1 PF IS7816 WT IS7816 CWT...

Страница 1163: ...es not result in the generation of an interrupt 1 The assertion of IS7816 BWT results in the generation of an interrupt 4 INITDE Initial Character Detected Interrupt Enable 0 The assertion of IS7816 I...

Страница 1164: ...ansmitted and the leading edge of the next response character has exceeded the programmed value This flag asserts only when C7816 TTYPE 0 This interrupt is cleared by writing 1 0 Wait time WT has not...

Страница 1165: ...al NACK detection counter is cleared and the count restarts from zero on the next received NACK This interrupt is cleared by writing 1 0 The number of retries and corresponding NACKS does not exceed t...

Страница 1166: ...only when C7816 TTYPE 1 See Wait time and guard time parameters 46 3 27 UART 7816 Wait N Register UARTx_WN7816 The WN7816 register contains a parameter that is used in the calculation of the guard tim...

Страница 1167: ...written to only when C7816 ISO_7816E is not set Address Base address 1Eh offset Bit 7 6 5 4 3 2 1 0 Read TXTHRESHOLD RXTHRESHOLD Write Reset 0 0 0 0 0 0 0 0 UARTx_ET7816 field descriptions Field Desc...

Страница 1168: ...te Reset 0 0 0 0 0 0 0 0 UARTx_TL7816 field descriptions Field Description 7 0 TLEN Transmit Length This value plus four indicates the number of characters contained in the block being transmitted Thi...

Страница 1169: ...816 TTYPE 0 See ATR Duration Time Counter 46 3 32 UART 7816 ATR Duration Timer Register B UARTx_AP7816B_T0 The AP7816B_T0 register contains variables used in the generation of the ATR Duration Timer T...

Страница 1170: ...I_H Write Reset 0 0 0 0 0 0 0 0 UARTx_WP7816A_T0 field descriptions Field Description 7 0 WI_H Wait Time Integer High C7816 TTYPE 0 Used to calculate the value used for the WT counter This register fi...

Страница 1171: ...0 Read WI_L Write Reset 0 0 0 1 0 1 0 0 UARTx_WP7816B_T0 field descriptions Field Description 7 0 WI_L Wait Time Integer Low C7816 TTYPE 0 Used to calculate the value used for the WT counter This regi...

Страница 1172: ...GI Write Reset 0 0 0 0 0 1 1 0 UARTx_WGP7816_T1 field descriptions Field Description 7 4 CWI1 Character Wait Time Integer 1 C7816 TTYPE 1 Used to calculate the value used for the CWT counter It repres...

Страница 1173: ...ters 46 4 Functional description This section provides a complete functional description of the UART block The UART allows full duplex asynchronous NRZ serial communication between the CPU and remote...

Страница 1174: ...IC TxD IRQ DMA LOGIC INFRARED LOGIC DMA Requests IRQ Requests TxD LOOP CONTROL LOOPS RSRC UART DATA REGISTER UART_D Figure 46 153 Transmitter Block Diagram 46 4 1 1 Transmitter character length The UA...

Страница 1175: ...value indicated by TWFIFO TXWATER The transmit driver routine may respond to this flag by writing additional datawords to the transmit buffer using C3 T8 D as space permits See Application information...

Страница 1176: ...he idle state even if there is data pending in the UART transmit data buffer To ensure that all the data written in the FIFO is transmitted on the link before clearing C2 TE wait for S1 TC to set Alte...

Страница 1177: ...TE during a transmission queues an idle character to be sent after the dataword currently being transmitted Note When queuing an idle character the idle character will be transmitted following the co...

Страница 1178: ...ins asserted for the whole time that the transmitter data buffer has any characters RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sen...

Страница 1179: ...ta buffer write CTS_B RTS_B C1 in transmission 1 1 Cn transmit characters Figure 46 154 Transmitter RTS and CTS timing diagram Chapter 46 Universal Asynchronous Receiver Transmitter UART K22F Sub Fami...

Страница 1180: ...C CONTROL RxD RxD LOOPS RSRC From Transmitter RECEIVER SOURCE CONTROL 7816 LOGIC To TxD INFRARED LOGIC Figure 46 155 UART receiver block diagram 46 4 2 1 Receiver character length The UART receiver ca...

Страница 1181: ...ter reception operates slightly differently Upon receipt of the parity bit the validity of the parity bit is checked If C7816 ANACK is set and the parity check fails or if INIT and the received charac...

Страница 1182: ...14 RT15 RT16 1 1 1 1 0 0 0 0 0 0 RT10 RT12 RT1 START BIT QUALIFICATION DATA SAMPLING START BIT VERIFICATION Figure 46 156 Receiver data sampling To verify the start bit and to detect noise data recove...

Страница 1183: ...is set enabled where the values of RT8 RT9 and RT10 exclusively determine if a start bit exists To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 The following...

Страница 1184: ...ts the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT R...

Страница 1185: ...T CLOCK 1 1 1 1 0 PERCEIVED AND ACTUAL START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT2 RT3 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 1 1 1 1 1 1 0 Figure 46 160...

Страница 1186: ...ere high SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RESET RT CLOCK 1 1 1 1 0 0 START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT10 RT1 RT2 RT3 1 1 1 1 1 0 0 1 0 1 RT4 RT5 RT6 RT7 RT8...

Страница 1187: ...The UART break character detection threshold depends on C1 M C1 PE S2 LBKDE and C4 M10 See the following table Table 46 163 Receive break character detection threshold LBKDE M M10 PE Threshold bits 0...

Страница 1188: ...data buffer is full or is overrun If the receiver request to send functionality is disabled the receiver RTS remains deasserted The following figure shows receiver hardware flow control functional ti...

Страница 1189: ...sing edge is not seen then the decoder sends a 1 to the receiver If the next bit is a 0 which arrives late then a low bit is detected according to Low bit detection The value sent to the receiver is c...

Страница 1190: ...les The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit data character with no errors is 154 147 154 100 4 54 For a 9 bit data character data sampling o...

Страница 1191: ...ceiver counts 170 RT cycles at the point when the count of the transmitting device is 176 RT cycles 11 bit times 16 RT cycles The maximum percent difference between the receiver count and the transmit...

Страница 1192: ...ion and the receivers for which the message is addressed process the frames that follow Any receiver for which a message is not addressed can set its C2 RWU and return to the standby state C2 RWU rema...

Страница 1193: ...red only on a match with either register Address match operation is not supported when C7816 ISO_7816E is set enabled 46 4 3 Baud rate generation A 13 bit modulus counter and a 5 bit fractional fine a...

Страница 1194: ...14 531 00000 0 19 209 0 1200 6 1200 0 11 1062 00000 0 9604 5 600 3 600 0 05 2125 00000 0 4800 0 300 0 300 0 00 4250 00000 0 2400 0 150 0 150 0 00 5795 00000 0 1760 1 110 0 110 0 00 Table 46 165 Baud...

Страница 1195: ...or 8 bit data characters that is eight bits are memory mapped in D A frame with eight data bits has a total of 10 bits The most significant bit of the eight data bits can be used as an address mark to...

Страница 1196: ...cter bits and a tenth internal data bit Note that if C4 M10 is set C1 PE must also be set In this case the tenth bit is the internally generated parity bit The ninth bit can either be used as an addre...

Страница 1197: ...4 4 3 2 Eight bit format with parity enabled BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT START BIT START BIT PARITY Figure 46 168 Seven bits of data with LSB first and parity BIT 6 BIT 5 BIT 4...

Страница 1198: ...0 PARITY STOP BIT START BIT START BIT BIT 8 ADDRESS MARK Figure 46 175 Nine bits of data with MSB first and parity 46 4 5 Single wire operation Normally the UART uses two pins for transmitting and re...

Страница 1199: ...he ISO 7816 protocol is an NRZ single wire half duplex interface The TxD pin is used in open drain mode because the data signal is used for both transmitting and receiving There are multiple subprotoc...

Страница 1200: ...essor with an interrupt if IE7816 INITDE is set Additionally the UART will alter S2 MSBF C3 TXINV and S2 RXINV automatically based on the initial character The corresponding initial character and resu...

Страница 1201: ...U in length The transmitter must wait for at least two time units ETU after detection of the error signal before attempting to retransmit the character It is assumed that the UART and the device smart...

Страница 1202: ...ration and violation detection of these settings On reset the wait time IS7816 WT defaults to 9600 ETUs and guard time GT to 12 ETUs These values are controlled by parameters in the WP7816 WN7816 and...

Страница 1203: ...esponding guard time expiring Table 46 169 Wait and guard time calculations Parameter Reset value ETU C7816 TTYPE 0 ETU C7816 TTYPE 1 ETU Wait time WT 9600 WI 480 Not used Character wait time CWT Not...

Страница 1204: ...feature is only supported in T 0 mode NOTE The ADT counter starts counting on detection of the complete TS Character It must be noted that by this time exactly 10 ETUs have elapsed since the start bit...

Страница 1205: ...e low pulses The infrared submodule receives its clock sources from the UART One of these two clocks are selected in the infrared submodule to generate either 3 16 1 16 1 32 or 1 4 narrow pulses durin...

Страница 1206: ...outlines additional details regarding the RXEDGIF interrupt because of its complexity of operation Any of the UART interrupt requests listed in the table can be used to bring the CPU out of Wait mode...

Страница 1207: ...the next cycle A rising edge is detected when the input is seen as a logic 0 during one module clock cycle and then a logic 1 during the next cycle 46 6 1 2 Clearing RXEDGIF interrupt request Writing...

Страница 1208: ...ments such as procedures to power up or power down the smartcard and when to take those actions are beyond the scope of this description To set up the UART for ISO 7816 operation 1 Select a baud rate...

Страница 1209: ...o set C2 RE 0 and C2 TE 0 The software should then adjust 7816 specific and UART generic parameters to match and configure data that was received during the answer on reset period After the new settin...

Страница 1210: ...block wait time and character wait times are not violated 46 8 2 Initialization sequence non ISO 7816 To initiate a UART transmission 1 Configure the UART a Select a baud rate Write this value to the...

Страница 1211: ...he mode of operation There may be implications that need to be carefully considered This section clarifies the behavior and the resulting implications Regardless of mode if a dataword is received whil...

Страница 1212: ...ome older implementations and is therefore supported for legacy reasons Applications that do not require this checking can simply clear S2 LBKDIF without checking the stored value to ensure it is a br...

Страница 1213: ...oltage levels of the UART s RTS and CTS signals TRANSMITTER UART RECEIVER TRANSMITTER UART RECEIVER TXD CTS_B RXD RTS_B RXD RTS_B TXD CTS_B Figure 46 180 Ready to receive The transmitter s CTS signal...

Страница 1214: ...of a bit time results in a pulse width of 1 6 s 46 8 8 Clearing 7816 wait timer WT BWT CWT interrupts The 7816 wait timer interrupts associated with IS7816 WT IS7816 BWT and IS7816 CWT will automatic...

Страница 1215: ...nsidered 1 Various reserved registers and register bits are used such as MSFB and M10 2 This module now generates an error when invalid address spaces are used 3 While documentation indicated otherwis...

Страница 1216: ...Application information K22F Sub Family Reference Manual Rev 3 7 2014 1216 Freescale Semiconductor Inc...

Страница 1217: ...ts operation in Stop modes Interrupt DMA or polled operation Transmit data register empty and transmission complete Receive data register full Receive overrun parity error framing error and noise erro...

Страница 1218: ...ode provided the asynchronous transmit and receive clock remains enabled The LPUART can generate an interrupt or DMA request to cause a wakeup from Stop mode 47 1 2 2 Wait mode The LPUART can be confi...

Страница 1219: ...rol Shift Enable Preamble All 1s Break All 0s LPUART Controls TxD TxD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE TE...

Страница 1220: ...to address outside the valid memory map will generate a bus error LPUART memory map Absolute address hex Register name Width in bits Access Reset value Section page 4002_A000 LPUART Baud Rate Register...

Страница 1221: ...a tenth bit to be part of the serial transmission This bit should only be changed when the transmitter and receiver are both disabled 0 Receiver and transmitter use 8 bit or 9 bit data characters 1 R...

Страница 1222: ...s input data using the rising and falling edge of the baud rate clock 16 RESYNCDIS Resynchronization Disable When set disables the resynchronization of the received data word when a data one followed...

Страница 1223: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE RAF TDRE TC RDRF IDLE OR NF FE PF W w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Bit...

Страница 1224: ...ive data not inverted 1 Receive data inverted 27 RWUID Receive Wake Up Idle Detect For RWU on idle character RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit For...

Страница 1225: ...ter active sending data a preamble or a break 1 Transmitter idle transmission activity complete 21 RDRF Receive Data Register Full Flag RDRF is set when the receive buffer LPUART_DATA is full To clear...

Страница 1226: ...character to be read from LPUART_DATA was received with noise detected within the character To clear NF write logic one to the NF 0 No noise detected 1 Noise detected in the received character in LPUA...

Страница 1227: ...ats When reading 9 bit or 10 bit data read R8 before reading LPUART_DATA T9 is the tenth data bit received when the LPUART is configured for 10 bit data formats When writing 10 bit data write T9 befor...

Страница 1228: ...is set 26 NEIE Noise Error Interrupt Enable This bit enables the noise flag NF to generate hardware interrupt requests 0 NF interrupts disabled use polling 1 Hardware interrupt requested when NF is se...

Страница 1229: ...y clears when an RWU event occurs that is an IDLE event when CTRL WAKE is clear or an address match when CTRL WAKE is set with STAT RWUID is clear NOTE RWU must be set only with CTRL WAKE 0 wakeup on...

Страница 1230: ...mode or single wire mode where transmitter outputs are internally connected to receiver input see RSRC bit 6 DOZEEN Doze Enable 0 LPUART is enabled in Doze mode 1 LPUART is disabled in Doze mode 5 RS...

Страница 1231: ...tically shifted after a received stop bit therefore resetting the idle count 0 Idle character bit count starts after start bit 1 Idle character bit count starts after stop bit 1 PE Parity Enable Enabl...

Страница 1232: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NOISY PARITYE FRETSC RXEMPT IDLINE 0 R9T9 R8T8 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0...

Страница 1233: ...ata returned on read is not valid 11 IDLINE Idle Line Indicates the receiver line was idle before receiving the character in DATA 9 0 Unlike the IDLE flag this bit can set for the first character rece...

Страница 1234: ...it is clear 15 10 Reserved This field is reserved This read only field is reserved and always has the value 0 9 0 MA1 Match Address 1 The MA1 and MA2 registers are compared to input data addresses whe...

Страница 1235: ...itter is idle 3 RXRTSE Receiver request to send enable Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun NOTE Do not set both RXRTSE and TXRTSE 0 Th...

Страница 1236: ...in CTS as a character is being sent do not affect its transmission 47 3 Functional description The LPUART supports full duplex asynchronous NRZ serial communication and comprises a baud rate generator...

Страница 1237: ...in the transmit data buffer Programs store data into the transmit data buffer by writing to the LPUART data register The central element of the LPUART transmitter is the transmit shift register that...

Страница 1238: ...ing error LPUART_STAT FE 1 occurs A break character can also be transmitted by writing to the LPUART_DATA register with bit 13 set and the data bits clear This supports transmitting the break characte...

Страница 1239: ...f CTS The transmitter s CTS signal can also be enabled even if the same LPUART receiver s RTS signal is disabled 47 3 2 3 Transceiver driver enable The transmitter can use LPUART_RTS as an enable sign...

Страница 1240: ...receive data register and the receive data register full LPUART_STAT RDRF status flag is set If LPUART_STAT RDRF was already set indicating the receive data register buffer was already full the overr...

Страница 1241: ...has been disabled This improves the reliability of the receiver in the presence of noise or mismatched baud rates It does not improve worst case analysis because some characters do not have any extra...

Страница 1242: ...acters 0 1 10 X1 Address match on and address match off IDLE flag set for discarded characters 47 3 3 2 1 Idle line wakeup When wake is cleared the receiver is configured for idle line wakeup In this...

Страница 1243: ...the LPUART_STAT RDRF flag In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time 47 3 3 2 3 Data match wakeup When LPUART_CTRL...

Страница 1244: ...ress and is compared with the associated MA1 or MA2 register The character is only transferred to the receive buffer and LPUART_STAT RDRF is set if the comparison matches All subsequent characters are...

Страница 1245: ...asserted until the transfer is complete even if the transmitter is disabled midway through a data transfer See Transceiver driver enable using LPUART_RTS for more details If the receiver request to s...

Страница 1246: ...a 0 which is sent to the receiver The decoder counter is also reset 47 3 3 4 4 High bit detection At OSR oversampling baud rate clocks after the previous rising edge if a rising edge is not seen then...

Страница 1247: ...rity and address mark wakeup so the ninth data bit can serve as the wakeup bit and the tenth bit as the parity bit In custom protocols the ninth and or tenth bits can also serve as software controlled...

Страница 1248: ...ata to the receiver When LPUART_CTRL TXDIR is set the LPUART_TX pin is an output driven by the transmitter the internal loop back connection is disabled and as a result the receiver cannot receive cha...

Страница 1249: ...cted for each one received A narrow low pulse is expected for a zero bit when LPUART_STAT RXINV is cleared while a narrow high pulse is expected for a zero bit when LPUART_STAT RXINV is set This recei...

Страница 1250: ...character that caused LPUART_STAT RDRF to be set the error flags noise flag LPUART_STAT NF framing error LPUART_STAT FE and parity error flag LPUART_STAT PF are set at the same time as LPUART_STAT RDR...

Страница 1251: ...tion of this chapter NOTE About data lines and audio channels Typically there are one or more data lines for TX and RX sides of the SAI peripheral depending on the device s design Each SAI data line m...

Страница 1252: ...ion Frame Sync Control Read FIFO Control FIFO Write FIFO Control Shift Register Bus Clock Audio Clock Bit Clock Bus Clock Transmitter Receiver Synchronous Mode SAI_TX_DATA SAI_TX_BCLK SAI_TX_SYNC SAI_...

Страница 1253: ...rame 48 1 3 3 Low leakage modes When entering low leakage modes the Stop Enable TCSR STOPE and RCSR STOPE bits are ignored and the SAI is disabled after completing the current transmit and receive Fra...

Страница 1254: ...rite access to an address from offset 0x108 and above will result in a bus error I2S memory map Absolute address hex Register name Width in bits Access Reset value Section page 4002_F000 SAI Transmit...

Страница 1255: ..._0000h 48 3 14 1273 4002_F094 SAI Receive Configuration 5 Register I2S0_RCR5 32 R W 0000_0000h 48 3 15 1275 4002_F0A0 SAI Receive Data Register I2S0_RDR0 32 R 0000_0000h 48 3 16 1275 4002_F0C0 SAI Rec...

Страница 1256: ...ables the transmitter When software clears this field the transmitter remains enabled and this bit remains set until the end of the current frame 0 Transmitter is disabled 1 Transmitter is enabled or...

Страница 1257: ...ffect 1 FIFO reset 24 SR Software Reset When set resets the internal transmitter logic including the FIFO pointers Software visible registers are not affected except for the status registers 0 No effe...

Страница 1258: ...IE Sync Error Interrupt Enable Enables disables sync error interrupts 0 Disables interrupt 1 Enables interrupt 10 FEIE FIFO Error Interrupt Enable Enables disables FIFO error interrupts 0 Disables the...

Страница 1259: ...scriptions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 0 TFW Transmit FIFO Watermark Configures the watermark level for all ena...

Страница 1260: ...elay the transmitter is clocked by the pad input as if the clock was externally generated This has the effect of decreasing the data input setup time but increasing the data output valid time The slav...

Страница 1261: ...read only field is reserved and always has the value 0 23 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 TCE Transmit Channel Enable Enables the corr...

Страница 1262: ...d that caused the FIFO error to set after the FIFO warning flag has been cleared 27 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 24 FPACK FIFO Pack...

Страница 1263: ...4 MF MSB First Configures whether the LSB or the MSB is transmitted first 0 LSB is transmitted first 1 MSB is transmitted first 3 FSE Frame Sync Early 0 Frame sync asserts with the first bit of the fr...

Страница 1264: ...th of less than 8 bits is not supported if there is only one word per frame 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 8 FBT First Bit Shifted...

Страница 1265: ...d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 WFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx_T...

Страница 1266: ...0 0 0 0 I2Sx_TMR field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 0 TWM Transmit Word Mask Configures whether...

Страница 1267: ...the receiver When software clears this field the receiver remains enabled and this bit remains set until the end of the current frame 0 Receiver is disabled 1 Receiver is enabled or receiver has been...

Страница 1268: ...No effect 1 FIFO reset 24 SR Software Reset Resets the internal receiver logic including the FIFO pointers Software visible registers are not affected except for the status registers 0 No effect 1 Sof...

Страница 1269: ...terrupts 0 Disables interrupt 1 Enables interrupt 10 FEIE FIFO Error Interrupt Enable Enables disables FIFO error interrupts 0 Disables the interrupt 1 Enables the interrupt 9 FWIE FIFO Warning Interr...

Страница 1270: ...ld descriptions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 0 RFW Receive FIFO Watermark Configures the watermark level for all...

Страница 1271: ...clocked by the pad input as if the clock was externally generated This has the effect of decreasing the data input setup time but increasing the data output valid time The slave mode timing from the d...

Страница 1272: ...erved This read only field is reserved and always has the value 0 23 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 RCE Receive Channel Enable Enable...

Страница 1273: ...FIFO error to set after the FIFO warning flag has been cleared 27 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 24 FPACK FIFO Packing Mode Enables p...

Страница 1274: ...always has the value 0 4 MF MSB First Configures whether the LSB or the MSB is received first 0 LSB is received first 1 MSB is received first 3 FSE Frame Sync Early 0 Frame sync asserts with the firs...

Страница 1275: ...one word per frame 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 8 FBT First Bit Shifted Configures the bit index for the first bit received for...

Страница 1276: ...4d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 WFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 RFP W Reset 0 0 0 0 0 0 0 0 0...

Страница 1277: ...receive FIFO for the corresponding word in the frame 0 Word N is enabled 1 Word N is masked 48 3 19 SAI MCLK Control Register I2Sx_MCR The MCLK Control Register MCR controls the clock source and direc...

Страница 1278: ...k 1 selected 10 MCLK divider input clock 2 selected 11 MCLK divider input clock 3 selected 23 0 Reserved This field is reserved This read only field is reserved and always has the value 0 48 3 20 SAI...

Страница 1279: ...er clock is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock The transmitter and receiver can independently select between the bus cl...

Страница 1280: ...ger divide ratios and will approach 50 50 for large non integer divide ratios There is no cycle to cycle jitter or duty cycle variance when the divide ratio is an integer or half integer otherwise the...

Страница 1281: ...t on system reset The SAI has a software reset and a FIFO reset 48 4 2 1 Software reset The SAI transmitter includes a software reset that resets all transmitter internal logic including the bit clock...

Страница 1282: ...eration In synchronous mode the receiver is enabled only when both the transmitter and receiver are enabled It is recommended that the transmitter is the last enabled and the first disabled If the rec...

Страница 1283: ...frame or asserts one bit early Assert for a duration between 1 bit clock and the first word length Frame length from 1 to 16 words per frame Word length to support 8 to 32 bits per word First word len...

Страница 1284: ...vidual write Note that 8 bit writes should only be used when transmitting up to 8 bit data and 16 bit writes should only be used when transmitting up to 16 bit data Writes to a TDR are ignored if the...

Страница 1285: ...ded at the start of each frame and after every second unmasked transmit word The first word transmitted is taken from 16 bit word at byte offset 0 first bit is selected by TCFG5 FBT must be configured...

Страница 1286: ...from stop mode 48 4 7 1 FIFO request flag The FIFO request flag is set based on the number of entries in the FIFO and the FIFO watermark configuration The transmit FIFO request flag is set when the nu...

Страница 1287: ...t order the transmitter will continue from the same word number in the frame that caused the FIFO to underflow but only after new data has been written to the transmit FIFO Software should still clear...

Страница 1288: ...When the sync error flag is set the transmitter or receiver continues checking for frame sync assertion when idle or at the end of each frame The sync error flag can generate an interrupt only 48 4 7...

Страница 1289: ...sponding Port Control and Interrupt module for that pin is enabled Efficient bit manipulation of the general purpose outputs is supported through the addition of set clear and toggle write only regist...

Страница 1290: ...escription I O PORTA31 PORTA0 General purpose input output I O PORTB31 PORTB0 General purpose input output I O PORTC31 PORTC0 General purpose input output I O PORTD31 PORTD0 General purpose input outp...

Страница 1291: ...ch port are implemented on each device See the chapter on signal multiplexing for the number of GPIO ports available in the device 49 2 Memory map and register definition Any read or write access to t...

Страница 1292: ...ort Clear Output Register GPIOC_PCOR 32 W always reads 0 0000_0000h 49 2 3 1294 400F_F08C Port Toggle Output Register GPIOC_PTOR 32 W always reads 0 0000_0000h 49 2 4 1295 400F_F090 Port Data Input Re...

Страница 1293: ...n registers associated with pins not available in your selected package All unbonded pins not available in your package will default to DISABLE state for lowest power consumption Address Base address...

Страница 1294: ...in PDORn is set to logic 1 49 2 3 Port Clear Output Register GPIOx_PCOR This register configures whether to clear the fields of PDOR Address Base address 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21...

Страница 1295: ...ailable in your selected package All unbonded pins not available in your package will default to DISABLE state for lowest power consumption Address Base address 10h offset Bit 31 30 29 28 27 26 25 24...

Страница 1296: ...a digital function and the corresponding Port Control and Interrupt module is enabled The Port Data Input registers return the synchronized pin state after any enabled digital filter in the Port Contr...

Страница 1297: ...o facilitate efficient bit manipulation on the general purpose outputs pin data set pin data clear and pin data toggle registers exist to allow one or more outputs within one port to be set cleared or...

Страница 1298: ...Functional description K22F Sub Family Reference Manual Rev 3 7 2014 1298 Freescale Semiconductor Inc...

Страница 1299: ...n test mode Testing is performed via a boundary scan technique as defined in the IEEE 1149 1 2001 standard All data input to and output from the JTAGC block is communicated in serial format 50 1 1 Blo...

Страница 1300: ...upports several IEEE 1149 1 2001 defined instructions as well as several public and private device specific instructions Refer to Table 50 3 for a list of supported instructions Bypass register bounda...

Страница 1301: ...ction register while the JTAGC is enabled Supported test instructions include EXTEST HIGHZ CLAMP SAMPLE and SAMPLE PRELOAD Each instruction defines the set of data register s that may operate and inte...

Страница 1302: ...Clock Input TCK is an input pin used to synchronize the test logic and control register access through the TAP 50 2 2 TDI Test data input Test Data Input TDI is an input pin that receives serial test...

Страница 1303: ...ogic Reset TAP controller states Synchronous entry into the Test Logic Reset state results in the IDCODE instruction being loaded on the falling edge of TCK Asynchronous entry into the Test Logic Rese...

Страница 1304: ...he PIN mirrors bits 9 0 of the SIM_SDID REVID field Please see the SIM_SDID register description for more detail DC Design Center Indicates the design center Value is 0x2C PIN Part Identification Numb...

Страница 1305: ...selected register starting with the least significant bit as illustrated in the following figure This applies for the instruction register test data registers and the bypass register Selected Registe...

Страница 1306: ...DR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 IR EXIT2 DR UPDATE DR UPDATE IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 50 4 IEEE 1149 1 2001 TAP controller finite state ma...

Страница 1307: ...9 1 2001 standard for more details All undefined opcodes are reserved Table 50 3 4 bit JTAG instructions Instruction Code 3 0 Instruction summary IDCODE 0000 Selects device identification register for...

Страница 1308: ...nstruction has two functions The SAMPLE portion of the instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cell...

Страница 1309: ...can register using the SAMPLE PRELOAD instruction before the selection of EXTEST EXTEST asserts the internal system reset for the MCU to force a predictable internal state while performing external bo...

Страница 1310: ...n The boundary scan register consists of this shift register chain and is connected between TDI and TDO when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are loaded The shift register chain contai...

Страница 1311: ...roller chapter In Device mode IRC48 operation section updated step 5 of IRC48 initialization code sequence to The USB clock source must choose the output of the divided clock by setting SIM_SOPT2 USBS...

Страница 1312: ...K22F Sub Family Reference Manual Rev 3 7 2014 1312 Freescale Semiconductor Inc...

Страница 1313: ...limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance m...

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