Freescale Semiconductor MK22FN256VDC12, Справочное руководство

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22.4.4.2 Peak request rates
The second performance metric is a measure of the number of DMA requests that can be
serviced in a given amount of time. For this metric, assume that the peripheral request
causes the channel to move a single internal peripheral bus-mapped operand to/from
internal SRAM. The same timing assumptions used in the previous example apply to this
calculation. In particular, this metric also reflects the time required to activate the
channel.
The eDMA design supports the following hardware service request sequence. Note that
the exact timing from Cycle 7 is a function of the response times for the channel's read
and write accesses. In the case of an internal peripheral bus read and internal SRAM
write, the combined data phase time is 4 cycles. For an SRAM read and internal
peripheral bus write, it is 5 cycles.
Table 22-294. Hardware service request process
Cycle Description
With internal peripheral
bus read and internal
SRAM write
With SRAM read and
internal peripheral bus
write
1 eDMA peripheral request is asserted.
2 The eDMA peripheral request is registered locally in the
eDMA module and qualified. TCD
n _CSR[START] bit initiated
requests start at this point with the registering of the user
write to TCD
n word 7.
3 Channel arbitration begins.
4 Channel arbitration completes. The transfer control descriptor
local memory read is initiated.
5–6 The first two parts of the activated channel's TCD is read from
the local memory. The memory width to the eDMA engine is
64 bits, so the entire descriptor can be accessed in four
cycles
7 The first system bus read cycle is initiated, as the third part of
the channel's TCD is read from the local memory. Depending
on the state of the crossbar switch, arbitration at the system
bus may insert an additional cycle of delay here.
8–11 8–12 The last part of the TCD is read in. This cycle represents the
first data phase for the read, and the address phase for the
destination write.
12 13 This cycle represents the data phase of the last destination
write.
13 14 The eDMA engine completes the execution of the inner minor
loop and prepares to write back the required TCD
n fields into
the local memory. The TCD n word 7 is read and checked for
channel linking or scatter/gather requests.
14 15 The appropriate fields in the first part of the TCD n are written
back into the local memory.
Table continues on the next page...
Chapter 22 Enhanced Direct Memory Access (eDMA)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
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